A FPGA-based feature extraction using reconfigurable rotated wavelet transform for various classification schemes

A novel approach of an embedded FPGA-based design for feature extraction using reconfigurable rotated wavelet transform (RWT) for various classification schemes is proposed. A new set of filter bank coefficients is generated by rotating a standard 1D discrete wavelet filter (DWF) in order to overcome shortcomings inherent in conventional ways of feature extraction such as discrete wavelet transform (DWT). We tested our approach by conducting a fault classification experiment using DWT and RWT for feature extraction. The DWT yields an accurate classification efficiency of 73.33%, while the RWT yields 86.67%. The proposed architecture consists of a datapath module, a controller module and ROM, which contains filter coefficients and input image pixel data. The datapath module performs the feature extraction in four orientations using only four multipliers and adders irrespective of the DWF employed. Despite being slightly more complex to execute, the results of the proposed RWT architecture are comparable with the existing DWT architectures in various aspects such as hardware resources, computational time and power consumption.