Equivalent driver model for fast system simulation

As the clock speed increases and rise time decreases, an accurate I/O driver model is crucial for robust system designs. Due to the runtime limitations, a full-blown driver circuit model is impractical for those designs that require numerous simulation runs. Take the high-speed Rambus memory channel design as an example. Thousands of data read and data write simulations were performed with various patterns, configurations, and comer models. Many complex interconnect models are included in the simulation decks, in the form of frequency-dependent, lossy, and coupled transmission lines [1]. The only nonlinear model that is present is either the memory controller circuitry for data write or RDRAM driver circuitry for data read simulations. This paper describes a reduced, but equivalent, RDRAM driver model that significantly speeds up the simulation time for Rambus memory channel designs. The concept of using a reduced model in place of a full-circuit model is not new [2]. This paper, however, chooses a model that consists of a simple level-1 transistor in parallel with a voltage-controlled current source. A systematic approach is shown that curvefits the I-V curve by a level-1 transistor and matches the load line by a current source. The reduced model thus obtained results in time-domain waveforms that are nearly identical to the full-circuit's. Finally, it is noted that the same procedures can be applied to derive reduced models for many nonlinear circuits.