On-Chip Communication Architectures: System on Chip Interconnect
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[1] Sujit Dey,et al. Design of high-performance system-on-chips using communication architecture tuners , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[2] Wu Ye,et al. An alternative architecture for on-chip global interconnect: segmented bus power modeling , 1998, Conference Record of Thirty-Second Asilomar Conference on Signals, Systems and Computers (Cat. No.98CH36284).
[3] Tughrul Arslan,et al. A novel bus encoding scheme from energy and crosstalk efficiency perspective for AMBA based generic SoC systems , 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.
[4] K. Lee,et al. Design of CMOS tapered buffer for minimum power-delay product , 1994, IEEE J. Solid State Circuits.
[5] Satoshi Tanaka,et al. Half-swing clocking scheme for 75% power saving in clocking circuitry , 1994 .
[6] Chung-Ping Chen,et al. A fast algorithm for optimal wire-sizing under Elmore delay model , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.
[7] M. Suzuoki,et al. Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor , 2006, IEEE Journal of Solid-State Circuits.
[8] Stafford E. Tavares,et al. Cryptanalysis of RC4-like Ciphers , 1998, Selected Areas in Cryptography.
[9] Ian O'Connor,et al. Optical solutions for system-level interconnect , 2004, SLIP '04.
[10] Kiyoung Choi,et al. Partial bus-invert coding for power optimization of application-specific systems , 2001, IEEE Trans. Very Large Scale Integr. Syst..
[11] Mary Jane Irwin,et al. Some issues in gray code addressing , 1996, Proceedings of the Sixth Great Lakes Symposium on VLSI.
[12] Andy D. Pimentel,et al. An IDF-based trace transformation method for communication refinement , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).
[13] Igor L. Markov,et al. Fixed-outline floorplanning: enabling hierarchical design , 2003, IEEE Trans. Very Large Scale Integr. Syst..
[14] Massoud Pedram,et al. ALBORZ: Address Level Bus Power Optimization , 2002, Proceedings International Symposium on Quality Electronic Design.
[15] Yan Zhang. Architecture and performance comparison of a statistic-based lottery arbiter for shared bus on chip , 2005, ASP-DAC '05.
[16] Robert W. Brodersen,et al. Design of system interface modules , 1992, 1992 IEEE/ACM International Conference on Computer-Aided Design.
[17] Frank Vahid,et al. An object-oriented communication library for hardware-software codesign , 1997, Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97.
[18] Yehea I. Ismail. On-chip inductance cons and pros , 2002, IEEE Trans. Very Large Scale Integr. Syst..
[19] M. Frank Chang. CDMA/FDMA-interconnects for future ULSI communications , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..
[20] L.W. Linholm,et al. An optimized output stage for MOS integrated circuits , 1975, IEEE Journal of Solid-State Circuits.
[21] Chita R. Das,et al. A low latency router supporting adaptivity for on-chip interconnects , 2005, Proceedings. 42nd Design Automation Conference, 2005..
[22] A. Deutsch,et al. Functional high-speed characterization and modeling of a six-layer copper wiring structure and performance comparison with aluminum on-chip interconnections , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).
[23] Nikil D. Dutt,et al. Adaptive low-power address encoding techniques using self-organizing lists , 2003, IEEE Trans. Very Large Scale Integr. Syst..
[24] Keith A. Jenkins,et al. Design guidelines for short, medium, and long on-chip interconnections , 1996 .
[25] Mary Jane Irwin,et al. Adapative Error Protection for Energy Efficiency , 2003, ICCAD 2003.
[26] Chi-Ying Tsui,et al. Saving power in the control path of embedded processors , 1994, IEEE Design & Test of Computers.
[27] Pasi Liljeberg,et al. Pipelined on-chip bus architecture with distributed self-timed control , 2003, Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on.
[28] John R. Koza,et al. Genetic programming - on the programming of computers by means of natural selection , 1993, Complex adaptive systems.
[29] Vishwani D. Agrawal,et al. A tutorial on the emerging nanotechnology devices , 2004, 17th International Conference on VLSI Design. Proceedings..
[30] J. Joyner,et al. Opportunities for reduced power dissipation using three-dimensional integration , 2002, Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No.02EX519).
[31] Yvon Savaria,et al. Parallel regeneration of interconnections in VLSI & ULSI circuits , 1993, 1993 IEEE International Symposium on Circuits and Systems.
[32] Andrew Seawright,et al. High-level Symbolic Construction Techniques for High Performance Sequential Synthesis , 1993, 30th ACM/IEEE Design Automation Conference.
[33] Chunjie Duan,et al. Exploiting crosstalk to speed up on-chip buses , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.
[34] Bruce Schneier,et al. Applied cryptography (2nd ed.): protocols, algorithms, and source code in C , 1995 .
[35] C.S. Chang,et al. Interconnection challenges and the National Technology Roadmap for Semiconductors , 1998, Proceedings of the IEEE 1998 International Interconnect Technology Conference (Cat. No.98EX102).
[36] Alan J. Hu,et al. High-Level specification and automatic generation of IP interface monitors , 2002, DAC '02.
[37] R. Schaller,et al. Technological innovation in the semiconductor industry: A case study of the International Technology Roadmap for Semiconductors (ITRS) , 2001, PICMET '01. Portland International Conference on Management of Engineering and Technology. Proceedings Vol.1: Book of Summaries (IEEE Cat. No.01CH37199).
[38] A. Grill,et al. High-efficiency, Ge-on-SOI lateral PIN photodiodes with 29 GHz bandwidth , 2004, Conference Digest [Includes 'Late News Papers' volume] Device Research Conference, 2004. 62nd DRC..
[39] Shashi Kumar,et al. Slack-time aware routing in NoC systems , 2005, 2005 IEEE International Symposium on Circuits and Systems.
[40] Charles J. Alpert,et al. Wire segmenting for improved buffer insertion , 1997, DAC.
[41] Doron A. Peled,et al. Combining partial order reductions with on-the-fly model-checking , 1994, Formal Methods Syst. Des..
[42] Nicolas Halbwachs,et al. Synchronous Programming of Reactive Systems , 1992, CAV.
[43] Peng Yang,et al. PowerViP: SoC power estimation framework at transaction level , 2006, Asia and South Pacific Conference on Design Automation, 2006..
[44] Ting-Yen Chiang,et al. Closed-form analytical thermal model for accurate temperature estimation of multilevel ULSI interconnects , 2003, 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).
[45] Wei-Chung Cheng,et al. Chromatic encoding: a low power encoding technique for digital visual interface , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.
[46] Manfred Glesner,et al. Bus-Based Communication Synthesis on System-Level , 1996, TODE.
[47] Wei-Chung Cheng,et al. Low power techniques for address encoding and memory allocation , 2001, Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455).
[48] Mario R. Casu,et al. On-chip transparent wire pipelining , 2004, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..
[49] B. Krauter,et al. Including inductive effects in interconnect timing analysis , 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).
[50] J.C. Campbell,et al. A silicon NMOS monolithically integrated optical receiver , 1997, IEEE Photonics Technology Letters.
[51] Rainer Leupers,et al. A modular simulation framework for architectural exploration of on-chip interconnection networks , 2003, First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721).
[52] M.A. Elgamel,et al. Interconnect noise analysis and optimization in deep submicron technology , 2003, IEEE Circuits and Systems Magazine.
[53] W. Steinhögl,et al. Size-dependent resistivity of metallic wires in the mesoscopic range , 2002 .
[54] Guy Gogniat,et al. Communication synthesis and HW/SW integration for embedded system design , 1998, Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98).
[55] Nihar R. Mahapatra,et al. Partitioned Hybrid Encoding to Minimize On-Chip Energy Dissipation ofWide Microprocessor Buses , 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).
[56] Jacob K. White,et al. FastCap: a multipole accelerated 3-D capacitance extraction program , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[57] Massoud Pedram,et al. Architectural energy optimization by bus splitting , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[58] Max Mühlhäuser,et al. On-chip communication topology synthesis for shared multi-bus based architecture , 2005, International Conference on Field Programmable Logic and Applications, 2005..
[59] D. Pehlke,et al. Extremely high-Q tunable inductor for Si-based RF integrated circuit applications , 1997, International Electron Devices Meeting. IEDM Technical Digest.
[60] Nikil D. Dutt,et al. System-level power-performance trade-offs in bus matrix communication architecture synthesis , 2006, Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06).
[61] Bruce Schneier,et al. Side Channel Cryptanalysis of Product Ciphers , 1998, J. Comput. Secur..
[62] Edward A. Lee,et al. Ptolemy: A Framework for Simulating and Prototyping Heterogenous Systems , 2001, Int. J. Comput. Simul..
[63] Miodrag Potkonjak,et al. MediaBench: a tool for evaluating and synthesizing multimedia and communications systems , 1997, Proceedings of 30th Annual International Symposium on Microarchitecture.
[64] Andrew R. Conn,et al. Optimization of custom MOS circuits by transistor sizing , 1996, ICCAD 1996.
[65] Sung-Mo Kang,et al. Coupling-driven signal encoding scheme for low-power interface design , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).
[66] Bing-Lin Gu,et al. Ab initio study of transport properties of multiwalled carbon nanotubes , 2005 .
[67] Hasan Amjad,et al. Programming a Symbolic Model Checker in a Fully Expansive Theorem Prover , 2003, TPHOLs.
[68] Kevin Skadron,et al. Odd/even bus invert with two-phase transfer for buses with coupling , 2002, ISLPED '02.
[69] Hiroyuki Arai,et al. Proximity coupled power combiner/divider using parasitic element , 1997, Proceedings of 1997 Asia-Pacific Microwave Conference.
[70] F. Layouni,et al. STBus transaction level models using SystemC 2.0 , 2004, Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004..
[71] Naehyuck Chang,et al. Bus encoding for low-power high-performance memory systems , 2000, DAC.
[72] Jörg Desel,et al. Free choice Petri nets , 1995 .
[73] Enrico Macii,et al. Energy-efficient bus encoding for LCD displays , 2004, GLSVLSI '04.
[74] Frank Vahid,et al. Techniques for reducing read latency of core bus wrappers , 2000, DATE '00.
[75] K. L. Shepard,et al. Noise in deep submicron digital design , 1996, ICCAD 1996.
[76] James Kao,et al. Subthreshold leakage modeling and reduction techniques , 2002, ICCAD 2002.
[77] S. Ramesh,et al. Automated synthesis of assertion monitors using visual specifications , 2005, Design, Automation and Test in Europe.
[78] E. Demaray,et al. A New Global Interconnect Paradigm: MIM Power-Ground Plane Capacitors , 2006, 2006 International Interconnect Technology Conference.
[79] K. O. Kenneth,et al. Design rules for improving predictability of on-chip antenna characteristics in the presence of other metal structures , 2005, Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005..
[80] Shekhar Borkar,et al. Obeying Moore's law beyond 0.18 micron [microprocessor design] , 2000, Proceedings of 13th Annual IEEE International ASIC/SOC Conference (Cat. No.00TH8541).
[81] Masahiro Fujita,et al. Irredundant address bus encoding techniques based on adaptive codebooks for low power , 2003, ASP-DAC '03.
[82] Edmund M. Clarke,et al. Model Checking , 1999, Handbook of Automated Reasoning.
[83] A. Naeemi,et al. On-Chip Interconnect Networks at the End of the Roadmap: Limits and Nanotechnology Opportunities , 2006, 2006 International Interconnect Technology Conference.
[84] D. F. Wong,et al. Simulated Annealing for VLSI Design , 1988 .
[85] M. Paniccia,et al. A high-speed silicon optical modulator based on a metal–oxide–semiconductor capacitor , 2004, Nature.
[86] Patrick Groeneveld,et al. Comparison of An Æthereal Network on Chip and A Traditional Interconnect for A Multi-Processor DVB-T System on Chip , 2006, 2006 IFIP International Conference on Very Large Scale Integration.
[87] Amit Goel,et al. Formal verification of an IBM CoreConnect processor local bus arbiter core , 2000, DAC.
[88] G. Duesberg,et al. Carbon nanotubes for interconnect applications , 2002, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..
[89] Kees Goossens,et al. A Router Architecture for Networks on Silicon , 2001 .
[90] Sunao Torii,et al. On-Chip Optical Interconnect , 2009, Proceedings of the IEEE.
[91] Tulika Mitra,et al. Using formal techniques to debug the AMBA system-on-chip bus protocol , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.
[92] Alex Doboli,et al. Layout conscious approach and bus architecture synthesis for hardware/software codesign of systems on chip optimized for speed , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[93] Vivek De,et al. Design and reliability challenges in nanometer technologies , 2004, Proceedings. 41st Design Automation Conference, 2004..
[94] H. B. Bakoglu,et al. Circuits, interconnections, and packaging for VLSI , 1990 .
[95] Larry R. Dalton,et al. Polymer micro-ring filters and modulators , 2002 .
[96] Chung-Kuan Cheng,et al. Optimal wire sizing and buffer insertion for low power and a generalized delay model , 1996 .
[97] Kathi Fisler. Towards Diagrammability and Efficiency in Event Sequence Languages , 2003, CHARME.
[98] William E. Weihl,et al. Lottery scheduling: flexible proportional-share resource management , 1994, OSDI '94.
[99] Youssef Saab,et al. Stochastic evolution: a fast effective heuristic for some generic layout problems , 1991, DAC '90.
[100] Giovanni De Micheli,et al. Automated composition of hardware components , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).
[101] D. Litaize,et al. Performance constraints for onchip optical interconnects , 2003 .
[102] Alain Greiner,et al. An Efficient TLM/T Modeling and Simulation Environment Based on Conservative Parallel Discrete Event Principles , 2006, Proceedings of the Design Automation & Test in Europe Conference.
[103] P. Burke. Luttinger liquid theory as a model of the gigahertz electrical properties of carbon nanotubes , 2002 .
[104] Gunar Schirner,et al. Accurate yet fast modeling of real-time communication , 2006, Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06).
[105] Nikil D. Dutt,et al. Fast exploration of bus-based on-chip communication architectures , 2004, International Conference on Hardware/Software Codesign and System Synthesis, 2004. CODES + ISSS 2004..
[106] Mario R. Casu,et al. Floorplanning for throughput , 2004, ISPD '04.
[107] Sung-Mo Kang,et al. Noise-aware power optimization for on-chip interconnect , 2000, ISLPED '00.
[108] Neil Savage,et al. Linking with light [high-speed optical interconnects] , 2002 .
[109] Dennis Sylvester,et al. Impact of small process geometries on microarchitectures in systems on a chip , 2001 .
[110] Martin E. Hellman,et al. On the security of multiple encryption , 1981, CACM.
[111] Mohamed I. Elmasry,et al. POMR: a power-aware interconnect optimization methodology , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[112] Jeffrey J. Tabor. Noise Reduction Using Low Weight and Constant Weight Coding Techniques , 1990 .
[113] A. Afzali-Kusha,et al. Serial Bus Encoding for Low Power Application , 2006, 2006 International Symposium on System-on-Chip.
[114] Jason Cong,et al. An interconnect energy model considering coupling effects , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[115] Hasan Amjad. Verification of AMBA Using a Combination of Model Checking and Theorem Proving , 2006, Electron. Notes Theor. Comput. Sci..
[116] Daniel Gajski,et al. Transaction level modeling: an overview , 2003, First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721).
[117] D. Albonesi,et al. On-Chip Copper-Based vs. Optical Interconnects: Delay Uncertainty, Latency, Power, and Bandwidth Density Comparative Predictions , 2006, 2006 International Interconnect Technology Conference.
[118] Alan J. Hu,et al. Monitor-Based Formal Specification of PCI , 2000, FMCAD.
[119] Natarajan Shankar,et al. Formal Verification for Fault-Tolerant Architectures: Prolegomena to the Design of PVS , 1995, IEEE Trans. Software Eng..
[120] Jason Cong,et al. Optimal wiresizing under Elmore delay model , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[121] Eun-Gu Jung,et al. High performance asynchronous bus for SoC , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..
[122] Jason Cong,et al. Simultaneous buffer and wire sizing for performance and power optimization , 1996, Proceedings of 1996 International Symposium on Low Power Electronics and Design.
[123] Jens Sparsø,et al. A router architecture for connection-oriented service guarantees in the MANGO clockless network-on-chip , 2005, Design, Automation and Test in Europe.
[124] Bruce A. Block,et al. High-speed CMOS-compatible photodetectors for optical interconnects , 2004, SPIE Optics + Photonics.
[125] Kaustav Banerjee,et al. Trends for ULSI Interconnections and Their Implications for Thermal, Reliability and Performance Issues (Invited Paper) , 2001 .
[126] Ganesh Gopalakrishnan,et al. Using live sequence charts for hardware protocol specification and compliance verification , 2001, Sixth IEEE International High-Level Design Validation and Test Workshop.
[127] H. Dai,et al. Can we achieve ultra-low resistivity in carbon nanotube-based metal composites? , 2004 .
[128] Martin Margala,et al. On-Chip Integrated Antennas - The First Challenge for Reliable on-Chip Wireless Interconnects , 2006, 2006 Canadian Conference on Electrical and Computer Engineering.
[129] Mani B. Srivastava,et al. A survey of techniques for energy efficient on-chip communication , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).
[130] Jörg Henkel,et al. An adaptive dictionary encoding scheme for SOC data buses , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.
[131] Ahmed Amine Jerraya,et al. Unified component integration flow for multi-processor SoC design and validation , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.
[132] Vwani P. Roychowdhury,et al. RF/wireless interconnect for inter- and intra-chip communications , 2001, Proc. IEEE.
[133] Eby G. Friedman,et al. Clock frequency and latency in synchronous digital systems , 1991, IEEE Trans. Signal Process..
[134] Horst Zimmermann,et al. Monolithic CMOS photoreceivers for short-range optical data communications , 1999 .
[135] Evangeline F. Y. Young,et al. Performance-driven register insertion in placement , 2004, ISPD '04.
[136] Reinaldo A. Bergamaschi,et al. Designing systems-on-chip using cores , 2000, DAC.
[137] Hsien-Hsin S. Lee,et al. Profile-guided microarchitectural floor planning for deep submicron processor design , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[138] Srivaths Ravi,et al. Security as a new dimension in embedded system design , 2004, Proceedings. 41st Design Automation Conference, 2004..
[139] G. Borriello,et al. Optimizing communication in embedded system co-simulation , 1997, Proceedings of 5th International Workshop on Hardware/Software Co Design. Codes/CASHE '97.
[140] Mircea R. Stan,et al. Two-dimensional codes for low power , 1996, Proceedings of 1996 International Symposium on Low Power Electronics and Design.
[141] Sujit Dey,et al. Fast performance analysis of bus-based system-on-chip communication architectures , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).
[142] Ajay Joshi,et al. Wave-pipelined multiplexed (WPM) routing for gigascale integration (GSI) , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[143] Dhiraj K. Pradhan,et al. Fault-tolerant computing : theory and techniques , 1986 .
[144] Larry Pileggi,et al. Coping with RC(L) interconnect design headaches , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).
[145] Petru Eles,et al. A formal verification methodology for IP-based designs , 2004 .
[146] A. Viterbi. CDMA: Principles of Spread Spectrum Communication , 1995 .
[147] William J. Dally,et al. Digital systems engineering , 1998 .
[148] Jacob K. White,et al. Layout techniques for minimizing on-chip interconnect self-inductance , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).
[149] Jürgen Becker,et al. Automated communication synthesis for architecture-precise rapid prototyping of real-time embedded systems , 2000, Proceedings 11th International Workshop on Rapid System Prototyping. RSP 2000. Shortening the Path from Specification to Prototype (Cat. No.PR00668).
[150] J.D. Meindl,et al. Optimal interconnection circuits for VLSI , 1985, IEEE Transactions on Electron Devices.
[151] G. Borriello,et al. Communication synthesis for distributed embedded systems , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).
[152] Alberto L. Sangiovanni-Vincentelli,et al. Convertibility verification and converter synthesis: two faces of the same coin , 2002, ICCAD 2002.
[153] Jason Cong,et al. Interconnect estimation and planning for deep submicron designs , 1999, DAC '99.
[154] Thomas A. Henzinger,et al. Interface automata , 2001, ESEC/FSE-9.
[155] Ivor Catt,et al. Crosstalk (Noise) in Digital Systems , 1967, IEEE Trans. Electron. Comput..
[156] Naresh R. Shanbhag,et al. Coding for reliable on-chip buses: fundamental limits and practical codes , 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.
[157] Fernando Gehm Moraes,et al. A Low Area Overhead Packet-switched Network on Chip: Architecture and Prototyping , 2003, VLSI-SOC.
[158] K. Banerjee,et al. A Comparative Scaling Analysis of Metallic and Carbon Nanotube Interconnections for Nanometer Scale VLSI Technologies , 2004 .
[159] Nikil D. Dutt,et al. Constraint-driven bus matrix synthesis for MPSoC , 2006, Asia and South Pacific Conference on Design Automation, 2006..
[160] Charles J. Alpert,et al. Interconnect synthesis without wire tapering , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[161] Patrice Godefroid,et al. Partial-Order Methods for the Verification of Concurrent Systems , 1996, Lecture Notes in Computer Science.
[162] Wayne Wolf,et al. Communication synthesis for distributed embedded systems , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).
[163] Andrew B. Kahng,et al. Delay models for MCM interconnects when response is nonmonotone , 1997, Proceedings 1997 IEEE Multi-Chip Module Conference.
[164] Ed F. Deprettere,et al. A trace transformation technique for communication refinement , 2001, CODES '01.
[165] P. Kapur,et al. Power comparison between high-speed electrical and optical interconnects for interchip communication , 2004, Journal of Lightwave Technology.
[166] G. De Micheli,et al. Performance driven reliable link design for networks on chips , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..
[167] Chia-Chih Yen,et al. On compliance test of on-chip bus for SOC , 2004 .
[168] W. C. Elmore. The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , 1948 .
[169] Nur A. Touba,et al. Weight-based codes and their application to concurrent error detection of multilevel circuits , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).
[170] Gunar Schirner,et al. Quantitative Analysis of Transaction Level Models for the AMBA Bus , 2006, Proceedings of the Design Automation & Test in Europe Conference.
[171] Cristina Silvano,et al. Power estimation of system-level buses for microprocessor-based architectures: a case study , 1999, Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040).
[172] K. Banerjee,et al. Global (interconnect) warming , 2001 .
[173] M. Edahiro,et al. Delay Minimization For Zero-skew Routing , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).
[174] William E. Donath,et al. Placement and average interconnection lengths of computer logic , 1979 .
[175] George Papadopoulos,et al. Full-wave PEEC time-domain method for the modeling of on-chipinterconnects , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[176] Trevor N. Mudge,et al. Power: A First-Class Architectural Design Constraint , 2001, Computer.
[177] Wayne P. Burleson,et al. Interconnect effort - a unification of repeater insertion and logical effort , 2003, IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings..
[178] Wayne P. Burleson,et al. Repeater insertion in deep sub-micron CMOS: ramp-based analytical model and placement sensitivity analysis , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).
[179] George Varghese,et al. Low-swing on-chip signaling techniques: effectiveness and robustness , 2000, IEEE Trans. Very Large Scale Integr. Syst..
[180] T. Sakurai,et al. Approximation of wiring delay in MOSFET LSI , 1983, IEEE Journal of Solid-State Circuits.
[181] Ivar Jacobson,et al. Object-Oriented Software Engineering , 1991, TOOLS.
[182] L. Sekaric,et al. Ultra-compact, low RF power, 10 Gb/s silicon Mach-Zehnder modulator. , 2007, Optics express.
[183] Nikil D. Dutt,et al. A Framework for Cosynthesis of Memory and Communication Architectures for MPSoC , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[184] S. Kim,et al. Fast capacitance extraction of general three-dimensional structures , 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.
[185] J. Meindl,et al. Compact physical models for multiwall carbon-nanotube interconnects , 2006, IEEE Electron Device Letters.
[186] Y. Savaria,et al. Circuit techniques for a 2 GHz AMBA AHB bus , 2005, The 3rd International IEEE-NEWCAS Conference, 2005..
[187] Vivek De,et al. Serial-link bus: a low-power on-chip bus architecture , 2005, ICCAD 2005.
[188] Sujit Dey,et al. FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology , 2005, Proceedings. 42nd Design Automation Conference, 2005..
[189] C.M. Lee,et al. An algorithm for CMOS timing and area optimization , 1984, IEEE Journal of Solid-State Circuits.
[190] Mahmut Kandemir,et al. Power protocol: reducing power dissipation on off-chip data buses , 2002, 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings..
[191] Luca Benini,et al. Simultaneous memory and bus partitioning for SoC architectures , 2005, Proceedings 2005 IEEE International SOC Conference.
[192] Kang G. Shin,et al. Static allocation of periodic tasks with precedence constraints in distributed real-time systems , 1989, [1989] Proceedings. The 9th International Conference on Distributed Computing Systems.
[193] David Blaauw,et al. DVS for on-chip bus designs based on timing error correction , 2005, Design, Automation and Test in Europe.
[194] Dr John Bainbridge. Asynchronous System-on-Chip Interconnect , 2002, Distinguished Dissertations.
[195] Cecilia Metra,et al. Bus crosstalk fault-detection capabilities of error-detecting codes for on-line testing , 1999, IEEE Trans. Very Large Scale Integr. Syst..
[196] Nikil D. Dutt,et al. ORB: An on-chip optical ring bus communication architecture for multi-processor systems-on-chip , 2008, 2008 Asia and South Pacific Design Automation Conference.
[197] Nihar R. Mahapatra,et al. Efficient encoding for address buses with temporal redundancy for simultaneous area and energy reduction , 2006, GLSVLSI '06.
[198] Nikil D. Dutt,et al. Memory system connectivity exploration , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.
[199] Martín Abadi,et al. A Theory of Objects , 1996, Monographs in Computer Science.
[200] Chita R. Das,et al. A hybrid SoC interconnect with dynamic TDMA-based transaction-less buses and on-chip networks , 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).
[201] Shyh-Chyi Wong,et al. Modeling of interconnect capacitance, delay, and crosstalk in VLSI , 2000 .
[202] Chunjie Duan,et al. Analysis and avoidance of cross-talk in on-chip buses , 2001, HOT 9 Interconnects. Symposium on High Performance Interconnects.
[203] Lorenzo Pavesi,et al. Routes toward silicon-based lasers , 2005 .
[204] Alberto L. Sangiovanni-Vincentelli,et al. Combining retiming and recycling to optimize the performance of synchronous circuits , 2003, 16th Symposium on Integrated Circuits and Systems Design, 2003. SBCCI 2003. Proceedings..
[205] Hoi-Jun Yoo,et al. SILENT: serialized low energy transmission coding for on-chip interconnection networks , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..
[206] Yu Mingyan,et al. The design of AMBA AHB/VCI wrapper , 2003, ASICON 2003.
[207] David Blaauw,et al. Driver modeling and alignment for worst-case delay noise , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).
[208] Paul Marchal,et al. Energy/Area/Delay Tradeoffs in the Physical Design of On-Chip Segmented Bus Architecture , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[209] Peter Petrov,et al. Low-power instruction bus encoding for embedded processors , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[210] Timo Hämäläinen,et al. Comparison of synthesized bus and crossbar interconnection architectures , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..
[211] James D. Meindl,et al. Compact distributed RLC interconnect models. I. Single line transient, time delay, and overshoot expressions , 2000 .
[212] Sérgio Vale Aguiar Campos,et al. Verifying the performance of the PCI local bus using symbolic techniques , 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.
[213] Charles J. Alpert,et al. Buffer insertion for noise and delay optimization , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[214] Ilan Beer,et al. RuleBase: an industry-oriented formal verification tool , 1996, DAC '96.
[215] Li-Fu Chang,et al. When should on-chip inductance modeling become necessary for VLSI timing analysis? , 2000, Proceedings of the IEEE 2000 International Interconnect Technology Conference (Cat. No.00EX407).
[216] Bill Moyer,et al. A low power unified cache architecture providing power and performance flexibility , 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).
[217] G. Craciun,et al. Through-wafer copper electroplating for three-dimensional interconnects , 2002 .
[218] Y. Savaria,et al. A beyond-1 GHz AMBA high-speed bus for SoC DSP platforms , 2004, Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004..
[219] Louis Scheffer. Methodologies and tools for pipelined on-chip interconnect , 2002, Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors.
[220] Mircea R. Stan,et al. Low-power encodings for global communication in CMOS VLSI , 1997, IEEE Trans. Very Large Scale Integr. Syst..
[221] Naresh R. Shanbhag,et al. Lower bounds on energy dissipation and noise-tolerance for deep submicron VLSI , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).
[222] Jan Madsen,et al. Communication estimation for hardware/software codesign , 1998, Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98).
[223] Qianfan Xu,et al. Micrometre-scale silicon electro-optic modulator , 2005, Nature.
[224] Ilan Beer,et al. FoCs: Automatic Generation of Simulation Checkers from Formal Specifications , 2000, CAV.
[225] Anantha Chandrakasan,et al. Reducing bus delay in submicron technology using coding , 2001, ASP-DAC '01.
[226] Kevin Skadron,et al. Compact thermal modeling for temperature-aware design , 2004, Proceedings. 41st Design Automation Conference, 2004..
[227] Hui Chen,et al. On-Chip Optical Interconnect Roadmap: Challenges and Critical Directions , 2005, IEEE Journal of Selected Topics in Quantum Electronics.
[228] Jia-Hung Lin,et al. Serial Low Power Bus Coding for VLSI , 2006, 2006 International Conference on Communications, Circuits and Systems.
[229] Behzad Razavi,et al. A comparison of electrical and optical clock networks in nanometer technologies , 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..
[230] Gaetano Borriello,et al. Dynamic communication models in embedded system co-simulation , 1997, DAC.
[231] Darko Kirovski,et al. Latency-driven design of multi-purpose systems-on-chip , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).
[232] Takayasu Sakurai,et al. Simple expressions for interconnection delay, coupling and crosstalk in VLSI's , 1991, 1991., IEEE International Sympoisum on Circuits and Systems.
[233] Soha Hassoun,et al. Optimal buffered routing path constructions for single and multiple clock domain systems , 2002, ICCAD 2002.
[234] Alex Doboli,et al. OSIRIS: automated synthesis of flat and hierarchical bus architectures for deep submicron systems on chip , 2004, IEEE Computer Society Annual Symposium on VLSI.
[235] Enrico Macii,et al. Wire placement for crosstalk energy minimization in address buses , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.
[236] André K. Nieuwland,et al. Why transition coding for power minimization of on-chip buses does not work , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.
[237] FrazerKen. Building secure software , 2002 .
[238] Venkata Krishnan,et al. PCI express and advanced switching: evolutionary path to building next generation interconnects , 2003, 11th Symposium on High Performance Interconnects, 2003. Proceedings..
[239] Sharon M. Weiss,et al. Temperature stability for silicon-based photonic band-gap structures , 2003 .
[240] Sudeep Pasricha. Transaction level modeling of SoC with SystemC 2.0 , 2004 .
[241] Tam-Anh Chu,et al. Synthesis of self-timed VLSI circuits from graph-theoretic specifications , 1987 .
[242] Wentai Liu,et al. Low-power design methodology for an on-chip with adaptive bandwidth capability , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).
[243] Rainer Leupers,et al. Retargetable generation of TLM bus interfaces for MP-SoC platforms , 2005, 2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05).
[244] Eby G. Friedman,et al. A unified design methodology for CMOS tapered buffers , 1995, IEEE Trans. Very Large Scale Integr. Syst..
[245] Jeffrey A. Davis,et al. Optimization of throughput performance for low-power VLSI interconnects , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[246] William John Bainbridge,et al. Asynchronous macrocell interconnect using MARBLE , 1998, Proceedings Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems.
[247] Markus G. Kuhn,et al. Tamper resistance: a cautionary note , 1996 .
[248] Y. Savaria,et al. A generic AHB bus for implementing high-speed locally synchronous islands , 2005, Proceedings. IEEE SoutheastCon, 2005..
[249] Ney Laert Vilar Calazans,et al. MAIA - a framework for networks on chip generation and verification , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..
[250] Pawan Kapur,et al. Power estimation in global interconnects and its reduction using a novel repeater optimization methodology , 2002, DAC '02.
[251] Ken Mai,et al. The future of wires , 2001, Proc. IEEE.
[252] Sujit Dey,et al. Configurable platforms with dynamic platform management: an efficient alternative to application-specific system-on-chips , 2004, 17th International Conference on VLSI Design. Proceedings..
[253] Thomas F. Melham,et al. An AMBA-ARM7 Formal Verification Platform , 2003, ICFEM.
[254] Sachin S. Sapatnekar,et al. RC Interconnect Optimization under the Elmore Delay Model , 1994, 31st Design Automation Conference.
[255] Hoi-Jun Yoo,et al. An arbitration look-ahead scheme for reducing end-to-end latency in networks on chip , 2005, 2005 IEEE International Symposium on Circuits and Systems.
[256] Young Hee Lee,et al. Crystalline Ropes of Metallic Carbon Nanotubes , 1996, Science.
[257] M.J. Kobrinsky,et al. Comparisons of conventional, 3-D, optical, and RF interconnects for on-chip clock distribution , 2004, IEEE Transactions on Electron Devices.
[258] Sujit Dey,et al. System-level performance analysis for designing on-chipcommunication architectures , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[259] Tobias Bjerregaard,et al. A survey of research and practices of Network-on-chip , 2006, CSUR.
[260] Jason Cong,et al. Interconnect sizing and spacing with consideration of couplingcapacitance , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[261] C. L. Liu,et al. A postprocessing algorithm for crosstalk-driven wire perturbation , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[262] Keith A. Jenkins,et al. When are transmission-line effects important for on-chip interconnections? , 1997 .
[263] Anantha P. Chandrakasan,et al. Low Power Digital CMOS Design , 1995 .
[264] Hiroto Yasuura,et al. A power reduction scheme for data buses by dynamic detection of active bits , 2003, Euromicro Symposium on Digital System Design, 2003. Proceedings..
[265] Mary Jane Irwin,et al. On-chip Bus Thermal Analysis and Optimization , 2006 .
[266] Andrew B. Kahng,et al. Tuning Strategies for Global Interconnects in High-Performance Deep-Submicron ICs , 1999, VLSI Design.
[267] Lorena Anghel,et al. Cost reduction and evaluation of temporary faults detecting technique , 2000, DATE '00.
[268] Srivaths Ravi,et al. Tamper resistance mechanisms for secure embedded systems , 2004, 17th International Conference on VLSI Design. Proceedings..
[269] Cheng-Kok Koh,et al. Flip-flop and repeater insertion for early interconnect planning , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.
[270] Alberto L. Sangiovanni-Vincentelli,et al. Theory of latency-insensitive design , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[271] T. Lee,et al. A 0.3-/spl mu/m CMOS 8-Gb/s 4-PAM serial link transceiver , 2000, 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326).
[272] Wei-Chung Cheng,et al. Power-optimal encoding for DRAM address bus (poster session) , 2000, ISLPED '00.
[273] Alberto L. Sangiovanni-Vincentelli,et al. On thermal effects in deep sub-micron VLSI interconnects , 1999, DAC '99.
[274] Mircea R. Stan,et al. Bus-invert coding for low-power I/O , 1995, IEEE Trans. Very Large Scale Integr. Syst..
[275] Randal E. Bryant,et al. Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.
[276] G. Schirner,et al. Fast and Accurate Transaction Level Models using Result Oriented Modeling , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.
[277] Kimiaki Shimokawa,et al. Reduction of wiring capacitance with new low dielectric SiOF interlayer film for high speed/low power sub-half micron CMOS , 1994, Proceedings of 1994 VLSI Technology Symposium.
[278] Jan Madsen,et al. Integrating communication protocol selection with hardware/software codesign , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[279] Sérgio Vale Aguiar Campos,et al. Symbolic Model Checking , 1993, CAV.
[280] E. Anderson,et al. Scanned probe microscopy of electronic transport in carbon nanotubes. , 2000, Physical review letters.
[281] Xiaoling Guo,et al. Propagation layers for intra-chip wireless interconnection compatible with packaging and heat removal , 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).
[282] Naresh R Shanbhag,et al. Achievable bounds on signal transition activity , 1997, ICCAD 1997.
[283] Lei He,et al. Simultaneous shield insertion and net ordering for capacitive and inductive coupling minimization , 2000, ISPD '00.
[284] Frédéric Pétrot,et al. A practical tool box for system level communication synthesis , 2001, Ninth International Symposium on Hardware/Software Codesign. CODES 2001 (IEEE Cat. No.01TH8571).
[285] Charlie Chung-Ping Chen,et al. Optimal wire-sizing formula under the Elmore delay model , 1996, DAC '96.
[286] A. Waizman,et al. Package capacitors impact on microprocessor maximum operating frequency , 2001, 2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220).
[287] Frank Vahid,et al. Interface exploration for reduced power in core-based systems , 1998, Proceedings. 11th International Symposium on System Synthesis (Cat. No.98EX210).
[288] F. MacWilliams,et al. The Theory of Error-Correcting Codes , 1977 .
[289] Yvon Savaria,et al. A novel 2 GHz multi-layer AMBA high-speed bus interconnect matrix for SoC platforms , 2005, 2005 IEEE International Symposium on Circuits and Systems.
[290] M. Paniccia,et al. A continuous-wave Raman silicon laser , 2005, Nature.
[291] L. Ivanov,et al. Modeling and analysis of noniterated systems: an approach based upon series-parallel posets , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).
[292] Enrico Macii,et al. Low-energy for deep-submicron address buses , 2001, ISLPED '01.
[293] Wolfgang Klingauf. Systematic transaction level modeling of embedded systems with SystemC , 2005, Design, Automation and Test in Europe.
[294] Armin Biere,et al. Symbolic Model Checking without BDDs , 1999, TACAS.
[295] Petru Eles,et al. Verification of embedded systems using a petri net based representation , 2000, ISSS '00.
[296] Luca Benini,et al. Error control schemes for on-chip communication links: the energy-reliability tradeoff , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[297] Axel Jantsch,et al. A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip , 2003, First IEEE/ACM/IFIP International Conference on Hardware/ Software Codesign and Systems Synthesis (IEEE Cat. No.03TH8721).
[298] Partha Pratim Pande,et al. Design of a switch for network on chip applications , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..
[299] Yehea I. Ismail,et al. Delayed line bus scheme: a low-power bus scheme for coupled on-chip buses , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).
[300] T. Heide,et al. Monolithic high-speed CMOS-photoreceiver , 1999, IEEE Photonics Technology Letters.
[301] Mahmut T. Kandemir,et al. A crosstalk aware interconnect with variable cycle transmission , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.
[302] Mahmut T. Kandemir,et al. Fault tolerant algorithms for network-on-chip interconnect , 2004, IEEE Computer Society Annual Symposium on VLSI.
[303] Charvaka Duvvury,et al. Trends for deep submicron VLSI and their implications for reliability , 1995, Proceedings of 1995 IEEE International Reliability Physics Symposium.
[304] Anantha Chandrakasan,et al. A bus energy model for deep submicron technology , 2002, IEEE Trans. Very Large Scale Integr. Syst..
[305] Eby G. Friedman,et al. Power characteristics of inductive interconnect , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[306] Naresh R. Shanbhag,et al. A coding framework for low-power address and data busses , 1999, IEEE Trans. Very Large Scale Integr. Syst..
[307] Eby G. Friedman,et al. A system for critical path analysis based on back annotation and distributed interconnect impedance models , 1988 .
[308] S. Ramesh,et al. CESC: a visual formalism for specification and verification of SoCs , 2004, GLSVLSI '04.
[309] Srinivasan Murali,et al. An Application-Specific Design Methodology for STbus Crossbar Generation , 2005, Design, Automation and Test in Europe.
[310] Jörg Henkel,et al. Fast cache and bus power estimation for parameterized system-on-a-chip design , 2000, DATE '00.
[311] Ganesh Lakshminarayana,et al. The LOTTERYBUS on-chip communication architecture , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[312] Jonathan Allen,et al. Waveform moment methods for improved interconnection analysis , 1990, 27th ACM/IEEE Design Automation Conference.
[313] Shannon V. Morton,et al. On-chip inductance issues in multiconductor systems , 1999, DAC '99.
[314] Narayanan Vijaykrishnan,et al. Simultaneous partitioning and frequency assignment for on-chip bus architectures , 2005, Design, Automation and Test in Europe.
[315] Massoud Pedram,et al. Transition reduction in memory buses using sector-based encoding techniques , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[316] Narayanan Vijaykrishnan,et al. Leakage-aware interconnect for on-chip network , 2005, Design, Automation and Test in Europe.
[317] Axel Jantsch,et al. A network on chip architecture and design methodology , 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.
[318] A. Deutsch,et al. Electrical characteristics of interconnections for high-performance systems , 1998, Proc. IEEE.
[319] William Stallings,et al. Cryptography and Network Security: Principles and Practice , 1998 .
[320] Dennis Sylvester,et al. Analytical modeling and characterization of deep-submicrometer interconnect , 2001 .
[321] David V. Plant,et al. Design rules for highly parallel free-Space optical interconnects , 2003 .
[322] Mehdi Hatamian,et al. Fundamental interconnection issues , 1987, AT&T Technical Journal.
[323] Lionel Torres,et al. Hardware engines for bus encryption: a survey of existing techniques , 2005, Design, Automation and Test in Europe.
[324] M. B. Srinivas,et al. Bus-encoding technique to reduce delay, power and simultaneous switching noise (SSN) in RLC interconnects , 2007, GLSVLSI '07.
[325] Wendong Hu,et al. NetBench: a benchmarking suite for network processors , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).
[326] Luca Benini,et al. ×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip , 2004, DATE.
[327] C. Duvvury,et al. ESD: a pervasive reliability concern for IC technologies , 1993 .
[328] P. K. Lala. Self-Checking and Fault-Tolerant Digital Design , 1995 .
[329] Akira Kanuma,et al. CMOS circuit optimization , 1983 .
[330] P. Burke,et al. Microwave transport in metallic single-walled carbon nanotubes. , 2005, Nano letters.
[331] Luca Benini,et al. Analyzing on-chip communication in a MPSoC environment , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.
[332] Alain Greiner,et al. Micro-network for SoC: implementation of a 32-port SPIN network , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.
[333] Andrew B. Kahng,et al. Interconnect tuning strategies for high-performance ICs , 1998, DATE.
[334] Arcot Sowmya,et al. Synchronous protocol automata: a framework for modelling and verification of SoC communication architectures , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.
[335] Soonhoi Ha,et al. Efficient exploration of bus-based system-on-chip architectures , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[336] Uriel Feige,et al. Exact analysis of hot-potato routing , 1992, Proceedings., 33rd Annual Symposium on Foundations of Computer Science.
[337] Kees G. W. Goossens,et al. An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network configuration , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.
[338] J. Meindl,et al. Monolayer metallic nanotube interconnects: promising candidates for short local interconnects , 2005, IEEE Electron Device Letters.
[339] David Blaauw,et al. Leakage-and crosstalk-aware bus encoding for total power reduction , 2004, Proceedings. 41st Design Automation Conference, 2004..
[340] Robert K. Brayton,et al. Retiming for DSM with area-delay trade-offs and delay constraints , 1999, DAC '99.
[341] A. Sugavanam,et al. On-chip antennas in silicon ICs and their application , 2005, IEEE Transactions on Electron Devices.
[342] Vaughan R. Pratt,et al. Modeling concurrency with partial orders , 1986, International Journal of Parallel Programming.
[343] Anand Raghunathan,et al. Power analysis of system-level on-chip communication architectures , 2004, International Conference on Hardware/Software Codesign and System Synthesis, 2004. CODES + ISSS 2004..
[344] Sujit Dey,et al. Efficient exploration of the SoC communication architecture design space , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).
[345] Michael D. Jones,et al. Formalization and Analysis of a Solution to the PCI 2.1 Bus Transaction Ordering Problem , 2000, Formal Methods Syst. Des..
[346] Nihar R. Mahapatra,et al. Energy-efficient compressed address transmission , 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.
[347] Natarajan Shankar,et al. Effective Theorem Proving for Hardware Verification , 1994, TPCD.
[348] Luca Benini,et al. Address bus encoding techniques for system-level power optimization , 1998, Proceedings Design, Automation and Test in Europe.
[349] Anantha P. Chandrakasan,et al. Low power bus coding techniques considering inter-wire capacitances , 2000, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).
[350] Larry Rudolph,et al. Creating a wider bus using caching techniques , 1995, Proceedings of 1995 1st IEEE Symposium on High Performance Computer Architecture.
[351] Kiyoung Choi,et al. Communication Architecture Synthesis of Cascaded Bus Matrix , 2007, 2007 Asia and South Pacific Design Automation Conference.
[352] Eui-Young Chung,et al. Fast and accurate transaction level modeling of an extended AMBA2.0 bus architecture , 2005, Design, Automation and Test in Europe.
[353] Charles A. Zukowski,et al. CMOS transistor sizing for minimization of energy-delay product , 1996, Proceedings of the Sixth Great Lakes Symposium on VLSI.
[354] Yehea I. Ismail,et al. The importance of including thermal effects in estimating the effectiveness of power reduction techniques , 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..
[355] Cristina Silvano,et al. Power optimization of system-level address buses based on software profiling , 2000, Proceedings of the Eighth International Workshop on Hardware/Software Codesign. CODES 2000 (IEEE Cat. No.00TH8518).
[356] Yu Cao,et al. Effects of global interconnect optimizations on performance estimation of deep submicron design , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).
[357] Kenneth L. McMillan,et al. Synthesizing converters between finite state protocols , 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.
[358] Chenming Hu,et al. Characterization of self-heating in advanced VLSI interconnect lines based on thermal finite element simulation , 1998 .
[359] Kyoung-Sun Jhang,et al. An improved implementation method of AHB BusMatrix , 2005, Proceedings 2005 IEEE International SOC Conference.
[360] T. Arslan,et al. An AMBA AHB-based reconfigurable SoC architecture using multiplicity of dedicated flyby DMA blocks , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..
[361] Prithviraj Banerjee,et al. Power aware interface synthesis for bus-based SoC designs , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.
[362] Kenneth L. McMillan,et al. Symbolic model checking: an approach to the state explosion problem , 1992 .
[363] Eui-Young Chung,et al. Fast exploration of parameterized bus architecture for communication-centric SoC design , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.
[364] J. Whinnery,et al. Dispersion of Picosecond Pulses in Coplanar Transmission Lines , 1986 .
[365] K. Yamashita,et al. Interconnect scaling scenario using a chip level interconnect model , 2000 .
[366] Yehea Ismail,et al. Figures of merit to characterize the importance of on-chip inductance , 1999 .
[367] Massoud Pedram,et al. Irredundant address bus encoding for low power , 2001, ISLPED '01.
[368] Jun Yang,et al. FV encoding for low-power data I/O , 2001, ISLPED '01.
[369] Naresh R. Shanbhag,et al. Coding for system-on-chip networks: a unified framework , 2005, IEEE Trans. Very Large Scale Integr. Syst..
[370] Ian O'Connor,et al. Heterogeneous modelling of an optical network-on-chip with SystemC , 2005, 16th IEEE International Workshop on Rapid System Prototyping (RSP'05).
[371] Pasquale Cocchini. A methodology for optimal repeater insertion in pipelined interconnects , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[372] C. Sharbono,et al. Factors affecting copper filling process within high aspect ratio deep vias for 3D chip stacking , 2006, 56th Electronic Components and Technology Conference 2006.
[373] Kjell O. Jeppson,et al. CMOS Circuit Speed and Buffer Optimization , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[374] Michael Kishinevsky,et al. Concurrent hardware : the theory and practice of self-timed design , 1993 .
[375] C. Svensson. Optimum voltage swing on on-chip and off-chip interconnects , 2000, Proceedings of the 26th European Solid-State Circuits Conference.
[376] William J. Dally,et al. Express Cubes: Improving the Performance of k-Ary n-Cube Interconnection Networks , 1989, IEEE Trans. Computers.
[377] K. Kim,et al. Wireless interconnection in a CMOS IC with integrated antennas , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).
[378] David M. Pozar,et al. Microwave and Rf Design of Wireless Systems , 2000 .
[379] Rajeev Alur,et al. Model-checking for real-time systems , 1990, [1990] Proceedings. Fifth Annual IEEE Symposium on Logic in Computer Science.
[380] Erwin A. de Kock,et al. Communication refinement in video systems on chip , 1999, CODES '99.
[381] Jason Cong,et al. Performance optimization of VLSI interconnect layout , 1996, Integr..
[382] Lionel Torres,et al. A parallelized way to provide data encryption and integrity checking on a processor-memory bus , 2006, 2006 43rd ACM/IEEE Design Automation Conference.
[383] M. Meyyappan,et al. Bottom-up approach for carbon nanotube interconnects , 2003 .
[384] Enrico Macii,et al. Combining wire swapping and spacing for low-power deep-submicron buses , 2003, GLSVLSI '03.
[385] Kees G. W. Goossens,et al. Networks on silicon: blessing or nightmare? , 2002, Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools.
[386] E.T. Lewis,et al. Optimization of device area and overall delay for CMOS VLSI designs , 1984, Proceedings of the IEEE.
[387] Daniel D. Gajski,et al. A novel memory size model for variable-mapping in system level design , 2004 .
[388] Cui Zhang,et al. A formal proof of absence of deadlock for any acyclic network of PCI buses , 1997 .
[389] Tomás Lang,et al. Working-zone encoding for reducing the energy in microprocessor address buses , 1998, IEEE Trans. Very Large Scale Integr. Syst..
[390] Hiroto Yasuura,et al. A bus delay reduction technique considering crosstalk , 2000, DATE '00.
[391] V. Kamakoti,et al. A bus encoding technique for power and cross-talk minimization , 2004, 17th International Conference on VLSI Design. Proceedings..
[392] Cheng-Kok Koh,et al. A high performance bus communication architecture through bus splitting , 2004 .
[393] Yuhen Hu,et al. Wave-pipelined on-chip global interconnect , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..
[394] Sani R. Nassif,et al. Optimal shielding/spacing metrics for low power design , 2003, IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings..
[395] Dirk Stroobandt,et al. A Priori Wire Length Estimates for Digital Design , 2001 .
[396] Vincenzo Catania,et al. Switching activity reduction in embedded systems: a genetic bus encoding approach , 2005 .
[397] S. R. Vemuru,et al. Variable-taper CMOS buffers , 1991 .
[398] Daniel Gajski,et al. Design and implementation of transducer for ARM-TMS communication , 2006, Asia and South Pacific Conference on Design Automation, 2006..
[399] M. Bohr. Interconnect scaling-the real limiter to high performance ULSI , 1995, Proceedings of International Electron Devices Meeting.
[400] Amer Baghdadi,et al. A generic wrapper architecture for multi-processor SoC cosimulation and design , 2001, CODES '01.
[401] A. Apsel,et al. Low-cost, high-efficiency, and high-speed SiGe phototransistors in commercial BiCMOS , 2006, IEEE Photonics Technology Letters.
[402] Arcot Sowmya,et al. Bridge over troubled wrappers:automated interface synthesis , 2004, 17th International Conference on VLSI Design. Proceedings..
[403] Lawrence T. Pileggi,et al. An interconnect channel design methodology for high performance integrated circuits , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.
[404] Kaustav Banerjee,et al. Compact modeling and SPICE-based simulation for electrothermal analysis of multilevel ULSI interconnects , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).
[405] Ahmed Amine Jerraya,et al. Scalable and flexible cosimulation of SoC designs with heterogeneous multi-processor target architectures , 2001, ASP-DAC '01.
[406] M. Meyyappan,et al. Carbon nanotube interconnects: a process solution , 2003, Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695).
[407] Christian Steger,et al. Energy estimation based on hierarchical bus models for power-aware smart cards , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.
[408] Jürgen Becker,et al. Communication Performance Models for Architecture-Precise Prototyping of Real-Time Embedded Systems , 2000, Des. Autom. Embed. Syst..
[409] Pasquale Cocchini. Concurrent flip-flop and repeater insertion for high performance integrated circuits , 2002, ICCAD 2002.
[410] Whitfield Diffie,et al. New Directions in Cryptography , 1976, IEEE Trans. Inf. Theory.
[411] Nikil D. Dutt,et al. COSMECA: Application Specific Co-Synthesis of Memory and Communication Architectures for MPSoC , 2006, Proceedings of the Design Automation & Test in Europe Conference.
[412] Jason Cong,et al. Simultaneous driver and wire sizing for performance and power optimization , 1994, IEEE Trans. Very Large Scale Integr. Syst..
[413] Miodrag Potkonjak,et al. Latency-guided on-chip bus network design , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).
[414] Jason Cong,et al. Multilevel global placement with retiming , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).
[415] Ashok V. Krishnamoorthy,et al. 1 Gbit/s CMOS photoreceiver with integrated detector operating at 850 nm , 1998 .
[416] Somesh Jha,et al. Verification of the Futurebus+ cache coherence protocol , 1993, Formal Methods Syst. Des..
[417] W. Liu,et al. Wave-pipelining: a tutorial and research survey , 1998, IEEE Trans. Very Large Scale Integr. Syst..
[418] Hannu Tenhunen,et al. Repeater insertion to minimise delay in coupled interconnects , 2001, VLSI Design 2001. Fourteenth International Conference on VLSI Design.
[419] B. Lengeler,et al. Transport in ropes of carbon nanotubes: Contact barriers and luttinger liquid theory , 2004 .
[420] Yehea I. Ismail,et al. Effects of inductance on the propagation delay and repeater insertion in VLSI circuits , 2000, IEEE Trans. Very Large Scale Integr. Syst..
[421] Naresh R. Shanbhag,et al. Toward achieving energy efficiency in presence of deep submicron noise , 2000, IEEE Trans. Very Large Scale Integr. Syst..
[422] Torsten Kempf,et al. A highly efficient modeling style for heterogeneous bus architectures , 2003, Proceedings. 2003 International Symposium on System-on-Chip (IEEE Cat. No.03EX748).
[423] Dexter Kozen,et al. RESULTS ON THE PROPOSITIONAL’p-CALCULUS , 2001 .
[424] Daniel Gajski,et al. Protocol Generation for Communication Channels , 1994, 31st Design Automation Conference.
[425] Dana Fisman,et al. The Temporal Logic Sugar , 2001, CAV.
[426] Charles E. Leiserson,et al. Fat-trees: Universal networks for hardware-efficient supercomputing , 1985, IEEE Transactions on Computers.
[427] P. McEuen,et al. Single-walled carbon nanotube electronics , 2002 .
[428] John Lillis,et al. Interconnect Analysis and Synthesis , 1999 .
[429] Mary Jane Irwin,et al. Transistor sizing for low power CMOS circuits , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[430] A. Sugavanam,et al. Wireless communication in a flip-chip package using integrated antennas on silicon substrates , 2005, IEEE Electron Device Letters.
[431] Kyoung-Rok Cho,et al. Modeling and analysis of the system bus latency on the SoC platform , 2006, SLIP '06.
[432] Gary McGraw,et al. Exploiting Software: How to Break Code , 2004 .
[433] A. Amerasekera,et al. The effect of interconnect scaling and low-k dielectric on the thermal characteristics of the IC metal , 1996, International Electron Devices Meeting. Technical Digest.
[434] C. Prunty,et al. Optimum tapered buffer , 1992 .
[435] Nikil D. Dutt,et al. Extending the transaction level modeling approach for fast communication architecture exploration , 2004, Proceedings. 41st Design Automation Conference, 2004..
[436] Anantha Chandrakasan,et al. Bus energy minimization by transition pattern coding (TPC) in deep sub-micron technologies , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).
[437] Jürgen Teich,et al. Packet routing in dynamically changing networks on chip , 2005, 19th IEEE International Parallel and Distributed Processing Symposium.
[438] Gary Mcgraw. Software security , 2004, IEEE Security & Privacy Magazine.
[439] Kaushik Roy,et al. Modeling of metallic carbon-nanotube interconnects for circuit simulations and a comparison with Cu interconnects for scaled technologies , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[440] J. Isoaho,et al. Refinement of on-chip communication channels , 2004, 2004 International Symposium on System-on-Chip, 2004. Proceedings..
[441] Kaustav Banerjee,et al. Performance analysis of carbon nanotube interconnects for VLSI applications , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..
[442] Gerard J. M. Smit,et al. An energy-efficient reconfigurable circuit-switched network-on-chip , 2005, 19th IEEE International Parallel and Distributed Processing Symposium.
[443] D. M. Brookes,et al. Protocol converter synthesis , 2004 .
[444] Abhijit Ghosh,et al. Methodology for hardware/software co-verification in C/C++ (short paper) , 2000, ASP-DAC '00.
[445] Brian Bell,et al. Repeater insertion and wire sizing optimization for throughput-centric VLSI global interconnects , 2002, ICCAD 2002.
[446] Donald E. Thomas,et al. Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC , 2007, 2007 5th IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).
[447] Luca Benini,et al. Performance Analysis of Arbitration Policies for SoC Communication Architectures , 2003, Des. Autom. Embed. Syst..
[448] Jason Cong,et al. An interconnect-centric design flow for nanometer technologies , 2001, Proc. IEEE.
[449] Yu Mingyan,et al. Designing AHB/PCI bridge , 2001, ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549).
[450] Vincent John Mooney,et al. A comparison of five different multiprocessor SoC bus architectures , 2001, Proceedings Euromicro Symposium on Digital Systems Design.
[451] F.J. Leonberger,et al. Optical interconnections for VLSI systems , 1984, Proceedings of the IEEE.
[452] Byung Kwan Park,et al. Highly Pipelined Bus : HiPi-Bus , 1991 .
[453] Eby G. Friedman,et al. Interconnect-Based Design Methodologies for Three-Dimensional Integrated Circuits , 2009, Proceedings of the IEEE.
[454] Alberto L. Sangiovanni-Vincentelli,et al. System-level design: orthogonalization of concerns andplatform-based design , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[455] Chuan Lin,et al. Retiming for wire pipelining in system-on-chip , 2004, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[456] J. Mehta,et al. Switching noise picked up by a planar dipole antenna mounted near integrated circuits , 2002 .
[457] Thorsten Grotker,et al. System Design with SystemC , 2002 .
[458] Cristina Silvano,et al. Power estimation for architectural exploration of HW/SW communication on system-level buses , 1999, CODES '99.
[459] H. Murata,et al. Rectangle-packing-based module placement , 1995, ICCAD 1995.
[460] B.L. Krauter,et al. Performance analysis of deep sub micron VLSI circuits in the presence of self and mutual inductance , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).
[461] Yvon Savaria,et al. Optimal methods of driving interconnections in VLSI circuits , 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.
[462] Yvon Savaria,et al. High-speed system bus for a SoC network processing platform , 2003, Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442).
[463] A. Kawabata,et al. Low-resistance multi-walled carbon nanotube vias with parallel channel conduction of inner shells [IC interconnect applications] , 2005, Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005..
[464] A. Zettl,et al. Thermal conductivity of single-walled carbon nanotubes , 1998 .
[465] Sujit Dey,et al. Evaluation of the traffic-performance characteristics of system-on-chip communication architectures , 2001, VLSI Design 2001. Fourteenth International Conference on VLSI Design.
[466] Tomás Lang,et al. Exploiting the locality of memory references to reduce the address bus energy , 1997, Proceedings of 1997 International Symposium on Low Power Electronics and Design.
[467] Taewhan Kim,et al. Coupling-aware high-level interconnect synthesis for low power , 2002, ICCAD 2002.
[468] Lawrence T. Pileggi,et al. Inductance 101: modeling and extraction , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).
[469] Uming Ko,et al. A repeater optimization methodology for deep sub-micron, high-performance processors , 1997, Proceedings International Conference on Computer Design VLSI in Computers and Processors.
[470] Brock J. LaMeres,et al. Encoding-based minimization of inductive cross-talk for off-chip data transmission , 2005, Design, Automation and Test in Europe.
[471] A. Farcy,et al. Design and performance of integrated antennas for wireless intra chip interconnections , 2006, IECON 2006 - 32nd Annual Conference on IEEE Industrial Electronics.
[472] Yehea I. Ismail,et al. A skewed repeater bus architecture for on-chip energy reduction in microprocessors , 2005, 2005 International Conference on Computer Design.
[473] Massoud Pedram,et al. Low power design methodologies , 1996 .
[474] C. Schönenberger,et al. Interference and Interaction in multi-wall carbon nanotubes , 1999, cond-mat/9905144.
[475] Edmund M. Clarke,et al. Design and Synthesis of Synchronization Skeletons Using Branching-Time Temporal Logic , 1981, Logic of Programs.
[476] Vittorio Zaccaria,et al. System Level Power Modeling and Simulation of High-End Industrial Network-On-Chip , 2004, Ultra Low-Power Electronics and Design.
[477] Andreas Gerstlauer,et al. Automatic Layer-Based Generation of System-On-Chip Bus Communication Models , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[478] Alain Greiner,et al. A generic architecture for on-chip packet-switched interconnections , 2000, DATE '00.
[479] Azad Naeemi,et al. Optimal global interconnects for GSI , 2003 .
[480] David M. Pozar,et al. Considerations for millimeter wave printed antennas , 1983 .
[481] Alberto L. Sangiovanni-Vincentelli,et al. Automatic synthesis of interfaces between incompatible protocols , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).
[482] Karem A. Sakallah,et al. Efficient Verification of the PCI Local Bus using Boolean Satisfiability , 2000 .
[483] J. Tatum. VCSELs for 10 GB/s optical interconnects , 2001, 2001 IEEE Emerging Technologies Symposium on BroadBand Communications for the Internet Era. Symposium Digest (Cat. No.01EX508).
[484] Keshab K. Parhi,et al. Reducing bus transition activity by limited weight coding with codeword slimming , 2000, ACM Great Lakes Symposium on VLSI.
[485] D. Neikirk,et al. Non-uniform lumped models for transmission line analysis , 1992, [1992 Proceedings] Electrical Performance of Electronic Packaging.
[486] Eby G. Friedman,et al. Optimum wire sizing of RLC interconnect with repeaters , 2004, Integr..
[487] Kaisa Sere,et al. From Action Systems to Modular Systems , 1994, Softw. Concepts Tools.
[488] Robert K. Brayton,et al. A novel VLSI layout fabric for deep sub-micron applications , 1999, DAC '99.
[489] Karem A. Sakallah,et al. GRASP—a new search algorithm for satisfiability , 1996, ICCAD 1996.
[490] C. G. Lin-Hendel. Accurate interconnect modeling for high frequency LSI/VLSI circuits and systems , 1990, Proceedings., 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors.
[491] Panduka Wijetunga. High-performance crossbar design for system-on-chip , 2003, The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings..
[492] Qing Wu,et al. Adaptive low-power bus encoding based on weighted code mapping , 2006, 2006 IEEE International Symposium on Circuits and Systems.
[493] David Samyde,et al. Side channel cryptanalysis , 2002 .
[494] Sachin S. Sapatnekar,et al. Designing optimized pipelined global interconnects: algorithms and methodology impact , 2005, 2005 IEEE International Symposium on Circuits and Systems.
[495] Mehdi Hatamian. Understanding Clock Skew in Synchronous Systems , 1988 .
[496] M. Hatamian,et al. Parallel bit-level pipelined VLSI designs for high-speed signal processing , 1987, Proceedings of the IEEE.
[497] P. S. Thiagarajan,et al. Message Sequence Charts , 2003, UML for Real.
[498] Sudhakar Yalamanchili,et al. Interconnection Networks: An Engineering Approach , 2002 .
[499] James D. Z. Ma,et al. Formulae and applications of interconnect estimation considering shield insertion and net ordering , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).
[500] Amir Pnueli. The Temporal Semantics of Concurrent Programs , 1981, Theor. Comput. Sci..
[501] Narayanan Vijaykrishnan,et al. A power estimation methodology for systemC transaction level models , 2005, 2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05).
[502] S. Tahar,et al. Design for verification of a PCI bus in SystemC , 2004, 2004 International Symposium on System-on-Chip, 2004. Proceedings..
[503] Enrico Macii,et al. Limited intra-word transition codes: an energy-efficient bus encoding for LCD display interfaces , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).
[504] Gabriel Robins,et al. Dynamically-wiresized Elmore-based routing constructions , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.
[505] R. Nunna,et al. Specification and formal verification of interconnect bus protocols , 2000, Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144).
[506] Qinru Qiu,et al. Partitioned bus coding for energy reduction , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..
[507] Sujit Dey,et al. Modeling and minimization of interconnect energy dissipation in nanometer technologies , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).
[508] Jörg Henkel,et al. Evaluating power consumption of parameterized cache and bus architectures in system-on-a-chip designs , 2001, IEEE Trans. Very Large Scale Integr. Syst..
[509] Anantha P. Chandrakasan,et al. Minimizing power consumption in digital CMOS circuits , 1995, Proc. IEEE.
[510] Clayton R. Paul,et al. Modeling of data bus structures using numerical methods , 1993, 1993 International Symposium on Electromagnetic Compatibility.
[511] Rudy Lauwereins,et al. Topology adaptive network-on-chip design and implementation , 2005 .
[512] Charles E. Leiserson,et al. Optimizing Synchronous Circuitry by Retiming (Preliminary Version) , 1983 .
[513] Bashir M. Al-Hashimi,et al. Minimization of crosstalk noise, delay and power using a modified bus invert technique , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.
[514] Eby G. Friedman,et al. Interconnect coupling noise in CMOS VLSI circuits , 1999, ISPD '99.
[515] Kurt Keutzer,et al. A global wiring paradigm for deep submicron design , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[516] David Blaauw,et al. Bus encoding for total power reduction using a leakage-aware buffer configuration , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[517] Hyuk-Jae Lee,et al. Design of AMBA/spl trade/ wrappers for multiple-clock operations , 2004, 2004 International Conference on Communications, Circuits and Systems (IEEE Cat. No.04EX914).
[518] Jeong-Gun Lee,et al. High performance asynchronous on-chip bus with multiple issue and out-of-order/in-order completion , 2005, GLSVLSI '05.
[519] Uri C. Weiser,et al. Interconnect-power dissipation in a microprocessor , 2004, SLIP '04.
[520] J.T. Alander,et al. On optimal population size of genetic algorithms , 1992, CompEuro 1992 Proceedings Computer Systems and Software Engineering.
[521] Soonhoi Ha,et al. Efficient exploration of on-chip bus architectures and memory allocation , 2004, International Conference on Hardware/Software Codesign and System Synthesis, 2004. CODES + ISSS 2004..
[522] Z. Navabi,et al. Evaluation of pseudo adaptive XY routing using an object oriented model for NOC , 2005, 2005 International Conference on Microelectronics.
[523] Eby G. Friedman,et al. Incorporating Voltage Fluctuations of the Power Distribution Network into the Transient Analysis of CMOS Logic Gates , 2002 .
[524] Nikil D. Dutt,et al. Formal performance evaluation of AMBA-based system-on-chip designs , 2006, EMSOFT '06.
[525] Luca Benini,et al. Power optimization of core-based systems by address bus encoding , 1998, IEEE Trans. Very Large Scale Integr. Syst..
[526] Min Tang,et al. Optimization of global interconnects in high performance VLSI circuits , 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).
[527] Shu Lin,et al. Error control coding : fundamentals and applications , 1983 .
[528] Rached Tourki,et al. Communication Architecture Synthesis for Multi-bus SoC , 2006 .
[529] Yehea Ismail,et al. On-Chip Inductance in High Speed Integrated Circuits , 2001 .
[530] Soo-Won Kim,et al. A multiprocessor server with a new highly pipelined bus , 1996, Proceedings of International Conference on Parallel Processing.
[531] M. Morse,et al. High speed silicon Mach-Zehnder modulator. , 2005, Optics express.
[532] Luca Benini,et al. Architectures and synthesis algorithms for power-efficient businterfaces , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[533] Alex Doboli,et al. Bus architecture synthesis for hardware-software co-design of deep submicron systems on chip , 2003, Proceedings 21st International Conference on Computer Design.
[534] Hugo De Man,et al. Minimizing the required memory bandwidth in VLSI system realizations , 1999, IEEE Trans. Very Large Scale Integr. Syst..
[535] Kees G. W. Goossens,et al. Networks on silicon: combining best-effort and guaranteed services , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.
[536] Alex Doboli,et al. Hardware-software co-design of resource constrained systems on a chip , 2004, 24th International Conference on Distributed Computing Systems Workshops, 2004. Proceedings..
[537] Puneet Gupta,et al. Wire swizzling to reduce delay uncertainty due to capacitive coupling , 2004, 17th International Conference on VLSI Design. Proceedings..
[538] H. Dai,et al. Quantum interference and ballistic transmission in nanotube electron waveguides. , 2001, Physical review letters.
[539] P. S. Thiagarajan,et al. Automatic generation of protocol converters from scenario-based specifications , 2004, 25th IEEE International Real-Time Systems Symposium.
[540] Niraj K. Jha,et al. A High-level Interconnect Power Model for Design Space Exploration , 2003, ICCAD 2003.
[541] Nikil Dutt,et al. FABSYN: floorplan-aware bus architecture synthesis , 2006 .
[542] Daniel P. Siewiorek,et al. Reliable Computer Systems: Design and Evaluation, Third Edition , 1998 .
[543] Jason Cong,et al. Buffer block planning for interconnect-driven floorplanning , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).
[544] Luca Benini,et al. Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based systems , 1997, Proceedings Great Lakes Symposium on VLSI.
[545] Tadao Murata,et al. Petri nets: Properties, analysis and applications , 1989, Proc. IEEE.
[546] Alain J. Martin. The limitations to delay-insensitivity in asynchronous circuits , 1990 .
[547] Herman Schmit,et al. A power aware system level interconnect design methodology for latency-insensitive systems , 2004, ICCAD 2004.
[548] William J. Dally,et al. Principles and Practices of Interconnection Networks , 2004 .
[549] Nikil D. Dutt,et al. Efficient power reduction techniques for time multiplexed address buses , 2002, 15th International Symposium on System Synthesis, 2002..
[550] Eby G. Friedman,et al. Clock distribution networks in synchronous digital integrated circuits , 2001, Proc. IEEE.
[551] Radu Marculescu,et al. System-level point-to-point communication synthesis using floorplanning information [SoC] , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.
[552] L. Ivanov,et al. Formal verification: a new partial order approach , 1999, Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454).
[553] Kaustav Banerjee,et al. A probabilistic framework for power-optimal repeater insertion in global interconnects under parameter variations , 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..
[554] M. Dresselhaus,et al. Carbon nanotubes : synthesis, structure, properties, and applications , 2001 .
[555] Chih-Ming Hung,et al. The feasibility of on-chip interconnection using antennas , 2005, ICCAD.
[556] Sujit Dey,et al. Performance analysis of systems with multi-channel communication architectures , 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.
[557] Gerard J. Holzmann,et al. The Model Checker SPIN , 1997, IEEE Trans. Software Eng..
[558] Mark A. Franklin,et al. Optimum buffer circuits for driving long uniform lines , 1991 .
[559] D. Fairbairn,et al. The VSI alliance : The journey from vision to production , 1998 .
[560] Ganesh Lakshminarayana,et al. LOTTERYBUS: a new high-performance communication architecture for system-on-chip designs , 2001, DAC '01.
[561] Taewhan Kim,et al. A systematic IP and bus subsystem modeling for platform-based system design , 2006, Proceedings of the Design Automation & Test in Europe Conference.
[562] Lawrence T. Pileggi,et al. Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization , 1993, 30th ACM/IEEE Design Automation Conference.
[563] John P. Fishburn,et al. Clock Skew Optimization , 1990, IEEE Trans. Computers.
[564] G.E. Moore,et al. Cramming More Components Onto Integrated Circuits , 1998, Proceedings of the IEEE.
[565] Ray T. Chen,et al. An optical centralized shared-bus architecture demonstrator for microprocessor-to-memory interconnects , 2003 .
[566] Sujit Dey,et al. Communication architecture tuners: a methodology for the design of high-performance communication architectures for system-on-chips , 2000, Proceedings 37th Design Automation Conference.
[567] Wayne Burleson,et al. Current sensing techniques for global interconnects in very deep submicron (VDSM) CMOS , 2001, Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems.
[568] Jason Cong,et al. Optimal wiresizing for interconnects with multiple sources , 1995, TODE.
[569] J. Meindl,et al. Design and Performance Modeling for Single-Walled Carbon Nanotubes as Local, Semiglobal, and Global Interconnects in Gigascale Integrated Systems , 2007, IEEE Transactions on Electron Devices.
[570] Roger D. Chamberlain,et al. Breaking the memory bottleneck with an optical data path , 2002, Proceedings 35th Annual Simulation Symposium. SS 2002.
[571] Sungpack Hong,et al. Decomposition of Bus-Invert Coding for Low-Power I/O , 2000, J. Circuits Syst. Comput..
[572] Magdy A. Bayoumi,et al. Dynamic fraction control bus: new SOC on-chip communication architecture design , 2005, Proceedings 2005 IEEE International SOC Conference.
[573] Lawrence T. Pileggi,et al. Moment-sensitivity-based wire sizing for skew reduction in on-chip clock nets , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[574] Saibal Mukhopadhyay,et al. Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits , 2003, Proc. IEEE.
[575] Chung-Hu Wu,et al. Accurate speed improvement techniques for RC line and tree interconnections in CMOS VLSI , 1990, IEEE International Symposium on Circuits and Systems.
[576] A. Kolodny,et al. Comparative analysis of serial vs parallel links in NoC , 2004, 2004 International Symposium on System-on-Chip, 2004. Proceedings..
[577] Malgorzata Marek-Sadowska,et al. Crosstalk in VLSI interconnections , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[578] A. Tuszynski,et al. CMOS tapered buffer , 1990 .
[579] Cecilia Metra,et al. Optimization of error detecting codes for the detection of crosstalk originated errors , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.
[580] M. Coppola,et al. Spidergon: a novel on-chip communication network , 2004, 2004 International Symposium on System-on-Chip, 2004. Proceedings..
[581] Orna Kupferman,et al. Module Checking , 1996, Inf. Comput..
[582] Ran Ginosar,et al. QNoC: QoS architecture and design process for network on chip , 2004, J. Syst. Archit..
[583] Daniel D. Gajski,et al. SPECC: Specification Language and Methodology , 2000 .
[584] Y. Kuroda,et al. NECoBus: a high-end SOC bus with a portable and low-latency wrapper-based interface mechanism , 2002, Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285).
[585] Eduard Cerny,et al. Compositional verification of an ATM switch module using interface recognizer/suppliers (IRS) , 2000, Proceedings IEEE International High-Level Design Validation and Test Workshop (Cat. No.PR00786).
[586] Tom Dhaene,et al. Selection of lumped element models for coupled lossy transmission lines , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[587] Stephen Phillips. VictoriaFalls: Scaling highly-threaded processor cores , 2007, 2007 IEEE Hot Chips 19 Symposium (HCS).
[588] Naresh R. Shanbhag,et al. A low-power bus design using joint repeater insertion and coding , 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..
[589] Andrew B. Kahng,et al. An analytical delay model for RLC interconnects , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[590] Axel Jantsch,et al. Guaranteed bandwidth using looped containers in temporally disjoint networks within the nostrum network on chip , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.
[591] Soonhoi Ha,et al. Schedule-aware performance estimation of communication architecture for efficient design space exploration , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[592] Kwang-Ting Cheng,et al. Pattern generation for delay testing and dynamic timing analysisconsidering power-supply noise effects , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[593] Eby G. Friedman,et al. Repeater design to reduce delay and power in resistive interconnect , 1998 .
[594] Alain Greiner,et al. SPIN: a scalable, packet switched, on-chip micro-network , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.
[595] Takayasu Sakurai,et al. Coupling-driven bus design for low-power application-specific systems , 2001, DAC '01.
[596] Sung-Mo Kang,et al. A low energy encoding technique for reduction of coupling effects in SoC interconnects , 2000, Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144).
[597] Jason Cong,et al. Interconnect performance estimation models for design planning , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[598] Nikil D. Dutt,et al. Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures , 2008, 21st International Conference on VLSI Design (VLSID 2008).
[599] Pascal Raymond. Recognizing Regular Expressions by Means of Dataflow Networks , 1996, ICALP.
[600] R. J. Antinone,et al. The modeling of resistive interconnects for integrated circuits , 1983 .
[601] Markus G. Kuhn,et al. Low Cost Attacks on Tamper Resistant Devices , 1997, Security Protocols Workshop.
[602] Igor L. Markov,et al. Error-correction and crosstalk avoidance in DSM busses , 2003, SLIP '03.
[603] Wei-Chung Cheng,et al. Software-only bus encoding techniques for an embedded system , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.
[604] M. Motomura,et al. Wrapper-based bus implementation techniques for performance improvement and cost reduction , 2004, IEEE Journal of Solid-State Circuits.
[605] Chia-Chih Yen,et al. Formal compliance verification of interface protocols , 2005, 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT)..
[606] N. Dutt,et al. Automated throughput-driven synthesis of bus-based communication architectures , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..
[607] Martin D. F. Wong,et al. Closed form solution to simultaneous buffer insertion/sizing and wire sizing , 1997, ISPD '97.
[608] Ali Afzali-Kusha,et al. A very high performance address BUS encoder , 2006, 2006 IEEE International Symposium on Circuits and Systems.
[609] Eby G. Friedman,et al. Delay uncertainty due to on-chip simultaneous switching noise in high performance CMOS integrated circuits , 2000, 2000 IEEE Workshop on SiGNAL PROCESSING SYSTEMS. SiPS 2000. Design and Implementation (Cat. No.00TH8528).
[610] Radu Marculescu,et al. DyAD - smart routing for networks-on-chip , 2004, Proceedings. 41st Design Automation Conference, 2004..
[611] Kaustav Banerjee,et al. A power-optimal repeater insertion methodology for global interconnects in nanometer designs , 2002 .
[612] Takayasu Sakurai,et al. Power distribution analysis of VLSI interconnects using model orderreduction , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[613] Nihar R. Mahapatra,et al. Dynamic address compression schemes: a performance, energy, and cost study , 2004, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..
[614] Lawrence T. Pileggi,et al. Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization , 1995, 32nd Design Automation Conference.
[615] Sujit Dey,et al. An Interconnect Architecture for Networking Systems on Chips , 2002, IEEE Micro.
[616] S. Wong,et al. Near speed-of-light signaling over on-chip electrical interconnects , 2003 .
[617] Janusz Zalewski. Advanced multimicroprocessor bus architectures , 1995 .
[618] Masahiro Fujita,et al. Symbolic model checking using SAT procedures instead of BDDs , 1999, DAC '99.
[619] Charlie Chung-Ping Chen,et al. Spec-based repeater insertion and wire sizing for on-chip interconnect , 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).
[620] Jürgen Teich,et al. DyNoC: A dynamic infrastructure for communication in dynamically reconfugurable devices , 2005, International Conference on Field Programmable Logic and Applications, 2005..
[621] Kwon,et al. Unusually high thermal conductivity of carbon nanotubes , 2000, Physical review letters.
[622] Mohamed Shalan,et al. DX-Gt: Memory Management and Crossbar Switch Generator for Multiprocessor System-on-a-Chip , 2002 .
[623] L.P.B. Katehi,et al. Si-micromachining in MM-wave circuits , 1997, 1997 Topical Symposium on Millimeter Waves. Proceedings (Cat. No.97TH8274).
[624] Hubert Kaeslin,et al. The Impact of Transistor Sizing on Power Efficiency in Submicron CMOS Circuits , 1996, ESSCIRC '96: Proceedings of the 22nd European Solid-State Circuits Conference.
[625] T. Sakurai,et al. Simple formulas for two- and three-dimensional capacitances , 1983, IEEE Transactions on Electron Devices.
[626] Julio A. de Oliveira Filho,et al. Petri net based interface analysis for fast IP-core integration , 2003, First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, 2003. MEMOCODE '03. Proceedings..
[627] David Blaauw,et al. Statistical estimation of leakage current considering inter- and intra-die process variation , 2003, ISLPED '03.
[628] G. Schindler,et al. Scaling laws for the resistivity increase of sub-100 nm interconnects , 2003, International Conference on Simulation of Semiconductor Processes and Devices, 2003. SISPAD 2003..
[629] K. Lee. On-chip interconnects: giga hertz and beyond , 1998, Proceedings of the IEEE 1998 International Interconnect Technology Conference (Cat. No.98EX102).
[630] Johnny Öberg,et al. Lowering power consumption in clock by using globally asynchronous locally synchronous design style , 1999, DAC '99.
[631] Frank Vahid,et al. Pre-fetching for improved core interfacing , 1999, Proceedings 12th International Symposium on System Synthesis.
[632] G. Edward Suh,et al. AEGIS: architecture for tamper-evident and tamper-resistant processing , 2003 .
[633] Chun-Gi Lyuh,et al. Low power bus encoding with crosstalk delay elimination [SoC] , 2002, 15th Annual IEEE International ASIC/SOC Conference.
[634] Masahiro Fujita,et al. An optimization of bus interconnects pitch for low-power and reliable bus encoding scheme , 2006, 2006 IEEE International Symposium on Circuits and Systems.
[635] K. Roy,et al. A circuit model for carbon nanotube interconnects: comparative study with Cu interconnects for scaled technologies , 2004, ICCAD 2004.
[636] Shinwook Kang,et al. Implementation of an on-chip bus bridge between heterogeneous buses with different clock frequencies , 2005, Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05).
[637] Guoqing Chen,et al. Low-power repeaters driving RC and RLC interconnects with delay and bandwidth constraints , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[638] Lei He,et al. Full-Chip Interconnect Power Estimation and Simulation Considering Concurrent Repeater and Flip-Flop Insertion , 2003, ICCAD 2003.
[639] Ahmed Amine Jerraya,et al. Mixed-level cosimulation for fine gradual refinement of communication in SoC design , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.
[640] Marco Pistore,et al. NuSMV 2: An OpenSource Tool for Symbolic Model Checking , 2002, CAV.
[641] Luca Benini,et al. Low power error resilient encoding for on-chip data buses , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.
[642] U. Ruckert,et al. High level estimation of the area and power consumption of on-chip interconnects , 2000, Proceedings of 13th Annual IEEE International ASIC/SOC Conference (Cat. No.00TH8541).
[643] Massoud Pedram,et al. Interconnect energy dissipation in high-speed ULSI circuits , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.
[644] L. Ivanov,et al. Formal Verification of Globally-Iterated/Locally-Non-Iterated Systems , 1999 .
[645] Diederik Verkest,et al. System-level interconnect architecture exploration for custom memory organizations , 2001, International Symposium on System Synthesis (IEEE Cat. No.01EX526).
[646] Malgorzata Marek-Sadowska,et al. Crosstalk Reduction by Transistor Sizing , 1999, ASP-DAC.
[647] Deepu Talla. An innovative HD video and digital image processor for low-cost digital entertainment products , 2007, 2007 IEEE Hot Chips 19 Symposium (HCS).
[648] Damien Lyonnard,et al. Exploiting TLM and Object Introspection for System-Level Simulation , 2006, Proceedings of the Design Automation & Test in Europe Conference.
[649] Alex Doboli,et al. Layout conscious bus architecture synthesis for deep submicron systems on chip , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.
[650] Naresh R. Shanbhag,et al. Area and energy-efficient crosstalk avoidance codes for on-chip buses , 2004, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..
[651] P. Yang,et al. Multilevel metal capacitance models for CAD design synthesis systems , 1992, IEEE Electron Device Letters.
[652] Sorin A. Huss,et al. Asynchronous wave pipelines for high throughput datapaths , 1998, 1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.98EX196).
[653] Luca P. Carloni,et al. On the Design of a Photonic Network-on-Chip , 2007, First International Symposium on Networks-on-Chip (NOCS'07).
[654] Andrew B. Kahng,et al. Interconnect optimization strategies for high-performance VLSI designs , 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).
[655] S. Datta. Electrical resistance: an atomistic view , 2004, cond-mat/0408319.
[656] Nikil D. Dutt,et al. Low power address encoding using self-organizing lists , 2001, ISLPED '01.
[657] A.M. Pappu,et al. A low power, low delay TIA for on-chip applications , 2005, (CLEO). Conference on Lasers and Electro-Optics, 2005..
[658] Andrew Lines. Nexus: an asynchronous crossbar interconnect for synchronous system-on-chip designs , 2003, 11th Symposium on High Performance Interconnects, 2003. Proceedings..
[659] H J Li,et al. Multichannel ballistic transport in multiwall carbon nanotubes. , 2005, Physical review letters.
[660] Chong Ser Choong,et al. A Vertical Wafer Level Packaging using Through Hole Filled Via Interconnects by Lift Off Polymer Method for MEMS and 3D Stacking Applications , 2005, Proceedings Electronic Components and Technology, 2005. ECTC '05..
[661] Xuan Zeng,et al. Power-Optimal Simultaneous Buffer Insertion/Sizing and Wire Sizing , 2003, ICCAD 2003.
[662] Jun Yang,et al. Frequent value encoding for low power data buses , 2004, TODE.
[663] P. McEuen,et al. Electron-Phonon Scattering in Metallic Single-Walled Carbon Nanotubes , 2003, cond-mat/0309641.
[664] Rainer Leupers,et al. A system level processor/communication co-exploration methodology for multi-processor system-on-chip platforms , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.
[665] Liang Deng,et al. Energy optimization in memory address bus structure for application-specific systems , 2005, ACM Great Lakes Symposium on VLSI.
[666] C. Svensson,et al. Principle of CMOS circuit power-delay optimization with transistor sizing , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.
[667] Niraj K. Jha,et al. Interconnect-aware high-level synthesis for low power , 2002, ICCAD 2002.
[668] Chi-Ying Tsui,et al. Re-configurable bus encoding scheme for reducing power consumption of the cross coupling capacitance for deep sub-micron instruction bus , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.
[669] M.-C. Shiau,et al. Delay models and speed improvement techniques for RC tree interconnections among small-geometry CMOS inverters , 1990 .
[670] Rainer Leupers,et al. Integrated system-level modeling of network-on-chip enabled multi-processor platforms , 2006 .
[671] Edmund M. Clarke,et al. Sequential circuit verification using symbolic model checking , 1991, DAC '90.
[672] Gaetano Borriello,et al. A geographically distributed framework for embedded system design and validation , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).
[673] Daniel Gajski,et al. Synthesis of system-level bus interfaces , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.
[674] Kees G. W. Goossens,et al. Networks on Chips for High-End Consumer-Electronics TV System Architectures , 2006, Proceedings of the Design Automation & Test in Europe Conference.
[675] Jörg Henkel,et al. A$^{\mbox{\huge\bf 2}}$BC: adaptive address bus coding for low power deep sub-micron designs , 2001, DAC '01.
[676] Frank Vahid,et al. The case for a configure-and-execute paradigm , 1999, Proceedings of the Seventh International Workshop on Hardware/Software Codesign (CODES'99) (IEEE Cat. No.99TH8450).
[677] Kurt Keutzer,et al. Bus encoding to prevent crosstalk delay , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).
[678] Takayasu Sakurai,et al. Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSIs , 1993 .
[679] TingTing Hwang,et al. A bus architecture for crosstalk elimination in high performance processor design , 2006, Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06).
[680] Srinivasan Murali,et al. SUNMAP: a tool for automatic topology selection and generation for NoCs , 2004, Proceedings. 41st Design Automation Conference, 2004..
[681] Petru Eles,et al. Simultaneous communication and processor voltage scaling for dynamic and leakage energy reduction in time-constrained systems , 2004, ICCAD 2004.
[682] Steven M. Nowick,et al. A low-latency FIFO for mixed-clock systems , 2000, Proceedings IEEE Computer Society Workshop on VLSI 2000. System Design for a System-on-Chip Era.
[683] Luca Benini,et al. System-level power optimization of special purpose applications: the Beach Solution , 1997, Proceedings of 1997 International Symposium on Low Power Electronics and Design.
[684] Sujit Dey,et al. Register transfer level power optimization with emphasis on glitch analysis and reduction , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[685] Michal Lipson,et al. All-optical switching on a silicon chip. , 2004, Optics letters.
[686] William J. Dally,et al. Route packets, not wires: on-chip inteconnection networks , 2001, DAC '01.
[687] Hoi-Jun Yoo,et al. An 800MHz star-connected on-chip network for application to systems on a chip , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..
[688] Hendrikus J. M. Veendrick,et al. Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits , 1984 .
[689] D.V. Plant. System design of chip and board level optical interconnects , 2004, Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting.
[690] M. Lipson,et al. Low-power-consumption short-length and high-modulation-depth silicon electrooptic modulator , 2003 .
[691] S. Taneja,et al. Transistor sizing for high performance and low power , 1997, Proceedings of CICC 97 - Custom Integrated Circuits Conference.
[692] F. Caignet,et al. The challenge of signal integrity in deep-submicrometer CMOS technology , 2001, Proc. IEEE.
[693] Xiaobo Sharon Hu,et al. A flexible framework for communication evaluation in SoC design , 2005, ASP-DAC '05.
[694] Jari Nurmi,et al. Issues in the development of a practical NoC: the Proteo concept , 2004, Integr..
[695] Daniel Gajski,et al. Interfacing Incompatible Protocols Using Interface Process Generation , 1995, 32nd Design Automation Conference.
[696] Fred B. Schneider,et al. Enforceable security policies , 2000, TSEC.
[697] Shuichi Sakai,et al. Bus Serialization for Reducing Power Consumption , 2006 .
[698] Paul Marchal,et al. Physical design implementation of segmented buses to reduce communication energy , 2006, Asia and South Pacific Conference on Design Automation, 2006..
[699] Qing Wu,et al. Low-power bus encoding using an adaptive hybrid algorithm , 2006, 2006 43rd ACM/IEEE Design Automation Conference.
[700] M.-C.F. Chang,et al. Advanced RF/baseband interconnect schemes for inter- and intra-ULSI communications , 2005, IEEE Transactions on Electron Devices.
[701] Arvin Park,et al. Dynamic base register caching: a technique for reducing address bus width , 1991, [1991] Proceedings. The 18th Annual International Symposium on Computer Architecture.
[702] Andreas Gerstlauer,et al. System Design - A Practical Guide with SpecC , 2001 .
[703] Niraj K. Jha,et al. MOCSYN: multiobjective core-based single-chip system synthesis , 1999, DATE '99.
[704] M. Kuhn,et al. The Advanced Computing Systems Association Design Principles for Tamper-resistant Smartcard Processors Design Principles for Tamper-resistant Smartcard Processors , 2022 .
[705] Fabien Castanier,et al. A flexible virtual platform for computational and communication architecture exploration of DMT VDSL modems , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.
[706] Jens Sparsø,et al. The MANGO clockless network-on-chip: Concepts and implementation , 2006 .
[707] Sachin S. Sapatnekar,et al. Exact and efficient crosstalk estimation , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[708] Gilles Kahn,et al. The Semantics of a Simple Language for Parallel Programming , 1974, IFIP Congress.
[709] Jan Madsen,et al. An approach to interface synthesis , 1995, Proceedings of the Eighth International Symposium on System Synthesis.
[710] Ganesh Gopalakrishnan,et al. A new partial order reduction algorithm for concurrent system verification , 1997 .
[711] Cheng-Kok Koh,et al. SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips , 2003, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[712] Gang Feng,et al. Optimized Design of Interconnected Bus on Chip for Low Power , 2006, First International Multi-Symposiums on Computer and Computational Sciences (IMSCCS'06).
[713] Eby G. Friedman,et al. Power Distribution Networks with On-Chip Decoupling Capacitors , 2007 .
[714] Giuseppe S. Garcea,et al. Simultaneous Analytic Area and Power Optimization for Repeater Insertion , 2003, ICCAD 2003.
[715] Mario R. Casu,et al. Throughput-driven floorplanning with wire pipelining , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[716] Subhrajit Bhattacharya,et al. Coral-automating the design of systems-on-chip using cores , 2000, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).
[717] L.P.P.P. van Ginneken,et al. Buffer placement in distributed RC-tree networks for minimal Elmore delay , 1990 .
[718] B. Floyd,et al. Jitter in a wireless clock distribution system , 2002, Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No.02EX519).
[719] Fernando Gehm Moraes,et al. HERMES: an infrastructure for low area overhead packet-switching networks on chip , 2004, Integr..
[720] Edmund M. Clarke,et al. Symbolic Model Checking: 10^20 States and Beyond , 1990, Inf. Comput..
[721] Nihar R. Mahapatra,et al. Accurate energy dissipation and thermal modeling for nanometer-scale buses , 2005, 11th International Symposium on High-Performance Computer Architecture.
[722] James D. Meindl,et al. Compact distributed RLC interconnect models-Part II: Coupled line transient expressions and peak crosstalk in multilevel networks , 2000 .
[723] Rajeev Murgai,et al. Using complementation and resequencing to minimize transitions , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).
[724] Kaustav Banerjee,et al. Interconnect limits on gigascale integration (GSI) in the 21st century , 2001, Proc. IEEE.
[725] Luca Benini,et al. Energy-efficient and reliable low-swing signaling for on-chip buses based on redundant coding , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).
[726] Asral Bahari,et al. Interframe Bus Encoding Technique for Low Power Video Compression , 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).
[727] Luciano Lavagno,et al. A region-based theory for state assignment in speed-independent circuits , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[728] Alice C. Parker,et al. SOS: Synthesis of application-specific heterogeneous multiprocessor systems , 2001, J. Parallel Distributed Comput..
[729] Jean-Didier Legat,et al. Enhancing security in the memory management unit , 1999, Proceedings 25th EUROMICRO Conference. Informatics: Theory and Practice for the New Millennium.
[730] P. Ajayan,et al. Reliability and current carrying capacity of carbon nanotubes , 2001 .
[731] E.M. Clarke,et al. Verifying IP-core based system-on-chip designs , 1999, Twelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454).
[732] Ahmed Amine Jerraya,et al. An optimal memory allocation for application-specific multiprocessor system-on-chip , 2001, International Symposium on System Synthesis (IEEE Cat. No.01EX526).
[733] Arvin Park,et al. Address compression through base register caching , 1990, [1990] Proceedings of the 23rd Annual Workshop and Symposium@m_MICRO 23: Microprogramming and Microarchitecture.
[734] Srivaths Ravi,et al. SECA: security-enhanced communication architecture , 2005, CASES '05.
[735] Wolfgang Rosenstiel,et al. SystemC: methodologies and applications , 2003 .
[736] A. Olugbon,et al. A Formal Approach to Virtualisation and Provisioning in AMBA AHB-based Reconfigurable Systems-on-Chip , 2005, 2005 International Symposium on System-on-Chip.
[737] P. Avouris,et al. Current saturation and electrical breakdown in multiwalled carbon nanotubes. , 2001, Physical review letters.
[738] S. Muthukumar,et al. Fabrication and electrical characterization of 3D vertical interconnects , 2006, 56th Electronic Components and Technology Conference 2006.
[739] Takayasu Sakurai,et al. A Unified Theory for Mixed CMOS / BiCMOS Buffer Optimization , 1991, ESSCIRC '91: Proceedings - Seventeenth European Solid-State Circuits Conference.
[740] Wolfgang Fichtner,et al. Self-timed ring for globally-asynchronous locally-synchronous systems , 2003, Ninth International Symposium on Asynchronous Circuits and Systems, 2003. Proceedings..
[741] Luca Benini,et al. On-Chip Communication Architectures: System on Chip Interconnect , 2008 .
[742] Xuan Zeng,et al. Power-optimal simultaneous buffer insertion/sizing and uniform wire sizing for single long wires , 2005, 2005 IEEE International Symposium on Circuits and Systems.
[743] Lei He,et al. Floorplanning optimization with trajectory piecewise-linear model for pipelined interconnects , 2004, Proceedings. 41st Design Automation Conference, 2004..
[744] A. Kawabata,et al. Carbon nanotube vias for future LSI interconnects , 2004, Proceedings of the IEEE 2004 International Interconnect Technology Conference (IEEE Cat. No.04TH8729).
[745] G. Mourou,et al. Terahertz attenuation and dispersion characteristics of coplanar transmission lines , 1991 .
[746] Miltos D. Grammatikakis,et al. Design of Cost-Efficient Interconnect Processing Units , 2008 .
[747] Paolo Crippa,et al. System-Level Power Analysis Methodology Applied to the AMBA AHB Bus , 2003, DATE.
[748] Vincent John Mooney,et al. Automated bus generation for multiprocessor SoC design , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[749] Payman Zarkesh-Ha,et al. Impact of three-dimensional architectures on interconnects in gigascale integration , 2001, IEEE Trans. Very Large Scale Integr. Syst..
[750] Stephen B. Furber,et al. Chain: A Delay-Insensitive Chip Area Interconnect , 2002, IEEE Micro.
[751] I. Verbauwhede,et al. CT-bus: a heterogeneous CDMA/TDMA bus for future SOC , 2004, Conference Record of the Thirty-Eighth Asilomar Conference on Signals, Systems and Computers, 2004..
[752] K. Carver,et al. Microstrip antenna technology , 1981 .
[753] K.K. O,et al. Design guidelines for reducing the impact of metal interference structures on the performance on-chip antennas , 2003, IEEE Antennas and Propagation Society International Symposium. Digest. Held in conjunction with: USNC/CNC/URSI North American Radio Sci. Meeting (Cat. No.03CH37450).
[754] Hasan Amjad. Model checking the AMBA protocol in HOL , 2004 .
[755] Jan Madsen,et al. Integrating communication protocol selection with partitioning in hardware/software codesign , 1998, Proceedings. 11th International Symposium on System Synthesis (Cat. No.98EX210).
[756] Massoud Pedram,et al. High-level power modeling, estimation, and optimization , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[757] Brock J. LaMeres,et al. Bus Stuttering : An Encoding Technique to Reduce Inductive Noise in Off-Chip Data Transmission , 2006, Proceedings of the Design Automation & Test in Europe Conference.
[758] Narayanan Vijaykrishnan,et al. Delay and energy efficient data transmission for on-chip buses , 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).
[759] Ronald L. Rivest,et al. Introduction to Algorithms , 1990 .
[760] Kiyoung Choi,et al. Interleaving partial bus-invert coding for low power reconfiguration of FPGAs , 1999, ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361).
[761] Nihar R. Mahapatra,et al. An accurate energy and thermal model for global signal buses , 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.
[762] Amer Baghdadi,et al. Automatic generation of application-specific architectures for heterogeneous multiprocessor system-on-chip , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).
[763] Yan Zhang,et al. Power and performance comparison of crossbars and buses as on-chip interconnect structures , 1999, Conference Record of the Thirty-Third Asilomar Conference on Signals, Systems, and Computers (Cat. No.CH37020).
[764] Nikil D. Dutt,et al. Floorplan-aware automated synthesis of bus-based communication architectures , 2005, Proceedings. 42nd Design Automation Conference, 2005..
[765] H. Yasuura,et al. A variation-aware low-power coding methodology for tightly coupled buses , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..
[766] Yao-Wen Chang,et al. RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[767] Srinivasa Vemuru,et al. Short-circuit power dissipation estimation for cmos logic gates , 1994 .