A radiation-hardened SOI-based FPGA

A radiation-hardened SRAM-based field programmable gate array VS1000 is designed and fabricated with a 0.5 m partial-depletion silicon-on-insulator logic process at the CETC 58th Institute. The new logic cell (LC), with a multi-mode based on 3-input look-up-table (LUT), increases logic density about 12% compared to a traditional 4-input LUT. The logic block (LB), consisting of 2 LCs, can be used in two functional modes: LUT mode and distributed read access memory mode. The hierarchical routing channel block and switch block can significantly improve the flexibility and routability of the routing resource. The VS1000 uses a CQFP208 package and contains 392 reconfigurable LCs, 112 reconfigurable user I/Os and IEEE 1149.1 compatible with boundary- scan logic for testing and programming. The function test results indicate that the hardware and software cooperate successfully and the VS1000 works correctly. Moreover, the radiation test results indicate that the VS1000 chip has total dose tolerance of 100 krad(Si), a dose rate survivability of 1.5 10 11 rad(Si)/s and a neutron fluence immunity of 1 10 14 n/cm 2 .

[1]  Y. Zorian,et al.  SRAM-based FPGA's: testing the LUT/RAM modules , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[2]  Yervant Zorian,et al.  RAM-based FPGAs: a test approach for the configurable logic , 1998, Proceedings Design, Automation and Test in Europe.

[3]  Yervant Zorian,et al.  Testing the configurable interconnect/logic interface of SRAM-based FPGA's , 1999, DATE '99.

[4]  S. Natarajan,et al.  A high density, low leakage, 5T SRAM for embedded caches , 2004, Proceedings of the 30th European Solid-State Circuits Conference.

[5]  Yervant Zorian,et al.  Test pattern and test configuration generation methodology for the logic of RAM-based FPGA , 1997, Proceedings Sixth Asian Test Symposium (ATS'97).

[6]  Yervant Zorian,et al.  SRAM-based FPGA's: testing the interconnect/logic interface , 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

[7]  Vaughn Betz,et al.  Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density , 1999, FPGA '99.

[8]  Ming Li,et al.  Automated test bitstream generation for an SOI-based FPGA , 2010, 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology.

[9]  Yervant Zorian,et al.  Test of RAM-based FPGA: methodology and application to the interconnect , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

[10]  Yu Hui,et al.  Design and Implementation of an FDP Chip , 2008 .