TECHNOLOGY Reviews on Algorithms and Architectures for Efficient Design of MIMO Accelerator

We surveyed about the design techniques of Multiple Input Multiple Output (MIMO) accelerator.The MIMO accelerator is a software programmable device that specializes in MIMO decoding and MIMO signal processing for Orthogonal Frequency Division Multiplexing systems(OFDM).It allows various algorithms to be easily implemented with a single hardware design. The accelerator is fully programmable within the domain of algorithms and functions needed to implement MIMO decoding for any arbitrary system or standards (i.e.,WiFi, LTE, etc.).To improve the system performance and reduce the complexity of the accelerator design some algorithms and architectures has been discussed here. The implementation of Field Programmable Gate Array(FPGA) architectures has been reviewed to minimize the overall energy/area consumption for the efficient design of accelerator hardware.

[1]  Babak Daneshrad,et al.  Energy Efficient Programmable MIMO Decoder Accelerator Chip in 65-nm CMOS , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Babak Daneshrad,et al.  A MIMO Decoder Accelerator for Next Generation Wireless Communications , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3]  Kavita Khare,et al.  Redesigned-Scale-Free CORDIC Algorithm Based FPGA Implementation of Window Functions to Minimize Area and Latency , 2012, Int. J. Reconfigurable Comput..

[4]  Babak Daneshrad,et al.  A Parameterized Programmable MIMO Decoding Architecture With a Scalable Instruction Set and Compiler , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  Lirida A. B. Naviner,et al.  Parallel scaling-free and area-time efficient CORDIC algorithm , 2012, 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012).

[6]  Shen-Fu Hsiao,et al.  Para-CORDIC: parallel CORDIC rotation algorithm , 2004, IEEE Trans. Circuits Syst. I Regul. Pap..

[7]  Babak Daneshrad,et al.  MIMO Accelerator: A design flow for a programmable MIMO decoder architecture , 2009, 2009 Conference Record of the Forty-Third Asilomar Conference on Signals, Systems and Computers.

[8]  S. Borkar,et al.  A 1.9 Gb/s 358 mW 16–256 State Reconfigurable Viterbi Accelerator in 90 nm CMOS , 2008, IEEE Journal of Solid-State Circuits.

[9]  C Paramasivam,et al.  Modified Scaling-Free Micro-RotationBased Circular CORDIC Algorithm UsingTaylor Series Expansion of Sine and Cosine , 2014 .