A dynamically reconfigurable communication architecture for multicore embedded systems

To deal with the communication bottleneck of multiprocessor systems, several communication architectures have been proposed in the last decade. Yet, none of them has demonstrated the performance of the direct connections between two communicating units. In this paper, we propose dynamically reconfigurable point-to-point (DRP2P) interconnects for setting up direct connection between two communicating units before the communication starts. DRP2P is neither point-to-point (P2P) nor Network-on-Chip (NoC); it stands between these two on-chip communication architectures. It is as fast as P2P and as scalable as NoC. Instead of using routers like in NoC, we utilize partial reconfiguration ability of FPGAs for routing data packets. Furthermore, DRP2P can work both on regular and irregular topologies. The only drawback of our approach is the reconfiguration latency. This drawback is completely hidden when the reconfiguration of the communication links is achieved during the computation times of the cores. DRP2P solves the scalability issue of P2P by setting up on-demand communication-specific links between cores. So, the occupied area and the total power consumption of communication architecture can be reduced significantly. We designed an on-chip self-reconfiguration core, c^2PCAP so as to achieve DRP2P interconnects as fast as possible. The c^2PCAP core is designed for Xilinx FPGAs and can partially reconfigure the FPGA at the highest rate proposed by the manufacturer (e.g. up to 400MB/s for Virtex-4).

[1]  Samuel Williams,et al.  The Landscape of Parallel Computing Research: A View from Berkeley , 2006 .

[2]  Jürgen Teich,et al.  DyNoC: A dynamic infrastructure for communication in dynamically reconfugurable devices , 2005, International Conference on Field Programmable Logic and Applications, 2005..

[3]  Marco Platzner,et al.  A Triple Hybrid Interconnect for Many-Cores: Reconfigurable Mesh, NoC and Barrier , 2010, 2010 International Conference on Field Programmable Logic and Applications.

[4]  Jürgen Teich,et al.  Platform-independent methodology for partial reconfiguration , 2004, CF '04.

[5]  Bin Zhang,et al.  A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput , 2008, 2008 International Conference on Field Programmable Logic and Applications.

[6]  João Canas Ferreira,et al.  Support for partial run-time reconfiguration of platform FPGAs , 2006, J. Syst. Archit..

[7]  Onchip Interconnect Exploration for Multicore Processors Utilizing FPGAs , 2006 .

[8]  Jürgen Becker,et al.  Exploitation of Run-Time Partial Reconfiguration for Dynamic Power Management in Xilinx Spartan III-based Systems , 2007, ReCoSoC.

[9]  Shurong Chen,et al.  Partial Reconfiguration Bitstream Compression for Virtex FPGAs , 2008, 2008 Congress on Image and Signal Processing.

[10]  Milan Vasilko,et al.  On Feasibility of FPGA Bitstream Compression During Placement and Routing , 2006, 2006 International Conference on Field Programmable Logic and Applications.

[11]  Morteza Saheb Zamani,et al.  Reducing reconfiguration time of reconfigurable computing systems in integrated temporal partitioning and physical design framework , 2006, Proceedings 20th IEEE International Parallel & Distributed Processing Symposium.

[12]  Fabrizio Petrini,et al.  Cell Multiprocessor Communication Network: Built for Speed , 2006, IEEE Micro.

[13]  François Duhem,et al.  FaRM: Fast Reconfiguration Manager for Reducing Reconfiguration Time Overhead on FPGA , 2011, ARC.

[14]  Axel Jantsch,et al.  Run-time Partial Reconfiguration speed investigation and architectural design space exploration , 2009, 2009 International Conference on Field Programmable Logic and Applications.

[15]  Hamid Sarbazi-Azad,et al.  Application-Aware Topology Reconfiguration for On-Chip Networks , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[16]  Arda Yurdakul,et al.  A self-reconfigurable platform for general purpose image processing systems on low-cost spartan-6 FPGAs , 2011, 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC).

[17]  Jim Tørresen,et al.  Advanced partial run-time reconfiguration on Spartan-6 FPGAs , 2010, 2010 International Conference on Field-Programmable Technology.

[18]  Zhiyuan Li,et al.  Configuration Compression for Virtex FPGAs , 2001, The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01).

[19]  C. Wang,et al.  Dynamic Reconfigurable Networks in NoC for I/O Supported Parallel Applications , 2010, 2010 10th IEEE International Conference on Computer and Information Technology.

[20]  Juanjo Noguera,et al.  Fast dynamic and partial reconfiguration data path with low hardware overhead on Xilinx FPGAs , 2010, 2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW).

[21]  Haibo Wang,et al.  A novel approach to minimizing reconfiguration cost for LUT-based FPGAs , 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

[22]  Abbes Amira,et al.  Efficient architectures for 3D HWT using dynamic partial reconfiguration , 2010, J. Syst. Archit..

[23]  S. Bayar,et al.  Self-reconfiguration on Spartan-III FPGAs with compressed partial bitstreams via a parallel configuration access port (cPCAP) core , 2008, 2008 Ph.D. Research in Microelectronics and Electronics.

[24]  Jürgen Becker,et al.  Exploitation of the External JTAG Interface for Internally Controlled Configuration Readback and Self-Reconfiguration of Spartan 3 FPGAs , 2008, 2008 IEEE Computer Society Annual Symposium on VLSI.

[25]  Stephan Wong,et al.  Partially reconfigurable point-to-point FPGA interconnects , 2008 .

[26]  Sergio López-Buedo,et al.  Self-Reconfigurable Embedded Systems on Low-Cost FPGAs , 2007, IEEE Micro.

[27]  D. J. A. Welsh,et al.  An upper bound for the chromatic number of a graph and its application to timetabling problems , 1967, Comput. J..

[28]  Srinivasan Murali,et al.  A Methodology for Mapping Multiple Use-Cases onto Networks on Chips , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[29]  Fernando Gehm Moraes,et al.  Infrastructure for dynamic reconfigurable systems: choices and trade-offs , 2006, SBCCI '06.

[30]  Jürgen Becker,et al.  Real-time LUT-based network topologies for dynamic and partial FPGA self-reconfiguration , 2004, Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784).

[31]  Markus Rullmann,et al.  A Reconfiguration Aware Circuit Mapper for FPGAs , 2007, 2007 IEEE International Parallel and Distributed Processing Symposium.

[32]  Dirk Stroobandt,et al.  RecoNoC: A reconfigurable network-on-chip , 2011, 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC).

[33]  Peter Green,et al.  Run-time support for dynamically reconfigurable computing systems , 2003, J. Syst. Archit..

[34]  Jürgen Teich,et al.  Bitstream Decompression for High Speed FPGA Configuration from Slow Memories , 2007, 2007 International Conference on Field-Programmable Technology.

[35]  Jürgen Becker,et al.  Implementation of a Virtual Internal Configuration Access Port (JCAP) for Enabling Partial Self-Reconfiguration on Xilinx Spartan III FPGAs , 2007, 2007 International Conference on Field Programmable Logic and Applications.

[36]  Sorin Cotofana,et al.  Bitstream compression techniques for Virtex 4 FPGAs , 2008, 2008 International Conference on Field Programmable Logic and Applications.

[37]  Radu Marculescu,et al.  System-Level Buffer Allocation for Application-Specific Networks-on-Chip Router Design , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[38]  Shaila Subbaraman,et al.  Internal Dynamic Partial Reconfiguration for Real Time Signal Processing on FPGA , 2010 .

[39]  Jens Sparsø,et al.  ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology , 2008, Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008).

[40]  Chris Jackson,et al.  Skip the Analysis: Self-Optimising Networks-on-Chip (Invited Paper) , 2010, 2010 International Symposium on Electronic System Design.

[41]  Yassin Elhillali,et al.  Trade-Off Exploration for Target Tracking Application in a Customized Multiprocessor Architecture , 2009, EURASIP J. Embed. Syst..

[42]  A. Yurdakul,et al.  Dynamic Partial Self-Reconfiguration on Spartan-III FPGAs via a Parallel Configuration Access Port ( PCAP ) , 2008 .

[43]  Radu Marculescu,et al.  Application-specific network-on-chip architecture customization via long-range link insertion , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

[44]  Ying Wang,et al.  A New Placement Approach to Minimizing FPGA Reconfiguration Data , 2008, 2008 International Conference on Embedded Software and Systems.

[45]  Viktor K. Prasanna,et al.  Configuration compression for FPGA-based embedded systems , 2005, IEEE Trans. Very Large Scale Integr. Syst..

[46]  Michael J. Wirthlin,et al.  Bitstream compression through frame removal and partial reconfiguration , 2009, 2009 International Conference on Field Programmable Logic and Applications.

[47]  Hamid Sarbazi-Azad,et al.  Virtual Point-to-Point Connections for NoCs , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[48]  Brent Nelson,et al.  PNoC: a flexible circuit-switched NoC for FPGA-based systems , 2006 .

[49]  Dirk Stroobandt,et al.  Automatically mapping applications to a self-reconfiguring platform , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.