Enhancing Fault Simulation Performance by Dynamic Fault Clustering

Fault simulation algorithms used for large designs propagate a list of faults instead of a single fault in each simulation. Concurrent (Ulrich and Baker, 1974) and deductive (Armstrong, 1972) fault simulation algorithms are two examples of this kind of algorithm. In this paper, we utilize an optimization concept, which can be added to fault list propagating algorithms. In this concept, faults can be grouped into several disjoint fault sets. All faults in a group affect every line of the circuit in a similar way. Fault clustering is performed dynamically, based on a particular test vector, during the fault simulation process. This method causes less memory fragmentation, since there are a limited number of fault groups in each simulation time. On the other hand, it reduces faulty circuit calculation in fault simulation process compared with the traditional fault simulation methods. In addition, the generality of this concept makes it useful for behavioral fault simulation methods as well as traditional gate-level ones. We have implemented this method in the VHDL environment and tested it on ISCAS'85 benchmarks. Experimental results show that in large circuits the performance is at least doubled by this technique

[1]  Silvano Gai,et al.  Fast differential fault simulation by dynamic fault ordering , 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[2]  Mani Soma,et al.  Fault bundling: reducing machine evaluation activity in hierarchical concurrent fault simulation , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[3]  Michael S. Hsiao,et al.  A new architectural-level fault simulation using propagation prediction of grouped fault-effects , 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.

[4]  Ernst G. Ulrich,et al.  Concurrent simulation of nearly identical digital networks , 1974, Computer.

[5]  Zainalabedin Navabi,et al.  Adaptation of an event-driven simulation environment to sequentially propagated concurrent fault simulation , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[6]  Douglas B. Armstrong,et al.  A Deductive Method for Simulating Faults in Logic Circuits , 1972, IEEE Transactions on Computers.

[7]  Zainalabedin Navabi,et al.  VHDL: Analysis and Modeling of Digital Systems , 1992 .

[8]  Kewal K. Saluja,et al.  Reduction of dynamic memory usage in concurrent fault simulation for synchronous sequential circuits , 1992, Proceedings First Asian Test Symposium (ATS `92).

[9]  Naoya Chujo,et al.  Accelerated fault simulation by propagating disjoint fault-sets , 1988, [1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.

[10]  Fabrizio Lombardi,et al.  Using RT Level Component Descriptions for Single Stuck-at Hierarchical Fault Simulation , 2004, J. Electron. Test..

[11]  Elizabeth M. Rudnick,et al.  Methods for reducing events in sequential circuit fault simulation , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[12]  Elizabeth M. Rudnick,et al.  Dynamic fault grouping for PROOFS: a win for large sequential circuits , 1997, Proceedings Tenth International Conference on VLSI Design.

[13]  Aiman H. El-Maleh,et al.  A static test compaction technique for combinational circuits based on independent fault clustering , 2003, 10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003.

[14]  Alfred V. Aho,et al.  Data Structures and Algorithms , 1983 .