论文信息 - 20 Gb/s Monolithic Integrated Clock Recovery and Data Decision

20 Gb/s Monolithic Integrated Clock Recovery and Data Decision

An IC for 20 Gb/s clock recovery and data decision was realised using 0.3 ¿m gate-length QW-HEMTs. A narrow-band regenerative frequency divider with on-chip resonator filters is used for the clock recovery. The parallel processing concept is accepted for the data decision. The complex IC was tested on wafer using 5 and 10-Gb/s input data. The desired 10-GHz clock signal and regenerated data signals have been obtained. The 2×2 mm2 IC has a power consumption of about 0.5 W at ¿3 volt supply voltage.

[1] Zhigong Wang,et al. Multi-Gb/s Silicon Bipolar Clock Recovery IC , 1991, IEEE J. Sel. Areas Commun..

[2] Z.-G. Wang,et al. 7.5 Gb/s Monolithically Integrated Clock Recovery using PLL and 0.3 μM Gate Length Quantum Well HEMTs , 1993, ESSCIRC '93: Nineteenth European Solid-State Circuits Conference.

[3] Zhigong Wang. MultiGbits/s data regeneration and clock recovery IC design , 1993 .

[4] M. Berroth,et al. 19 GHz monolithic integrated clock recovery using PLL and 0.3 /spl mu/m gate-length quantum-well HEMTs , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

[5] D. Clawin,et al. 5-Gbit/s Si integrated regenerative demultiplexer and decision circuit , 1987 .