Power-speed Trade-off in Parallel Prefix Circuits

Optimizing area and speed in parallel prefix circuits have been considered important for long time. The issue of power consumption in these circuits, however, has not been addressed. This dissertation presents a comparative study of different parallel prefix circuits from the point of view of power-speed trade-off. The power consumption and the power-delay product of seven parallel prefix circuits were compared. A linear output capacitance assumption, combined with PSpice simulations, is used to investigate the power consumption in the circuits. The degrees of freedom studied include different parallel prefix algorithms and voltage scaling. The results show that the use of the linear output capacitance assumption provides results that are consistent with those obtained using PSpice simulations. Because of the size-depth trade-off characteristic of prefix circuits, the results also show that parallelism of prefix circuits at a certain level coupled with the use of low supply voltage can be used to reduce the power-delay product to attain a desired throughput beyond the minimum possible. The study enables us to understand the power consumption behavior of prefix circuits, and to pick the suitable prefix circuit for the acceptable power consumption in the prefix with a given throughput. Circuit designers can then choose the best prefix circuit for a particular application.

[1]  Richard Brent.  On the Addition of Binary Numbers , 1970, IEEE Transactions on Computers.

[2]  Rajesh K. Mansharamani.  Parallel Computing Using the Prefix Problem , 1995 .

[3]  Magdy A. Bayoumi,et al.  A low power 10-transistor full adder cell for embedded architectures , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[4]  Yuke Wang,et al.  Design and analysis of 10-transistor full adders using novel XOR-XNOR gates , 2000, WCC 2000 - ICSP 2000. 2000 5th International Conference on Signal Processing Proceedings. 16th World Computer Congress 2000.

[5]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[6]  R. Frowd,et al.  The rise of energy delivery management systems , 2001, 2001 IEEE/PES Transmission and Distribution Conference and Exposition. Developing New Perspectives (Cat. No.01CH37294).

[7]  Yen-Chun Lin,et al.  A New Class of Depth-Size Optimal Parallel Prefix Circuits , 2004, The Journal of Supercomputing.

[8]  M. Sebastian.  Application-specific integrated circuits , 1997 .

[9]  Robert L. Boylestad.  Introductory Circuit Analysis , 1990 .

[10]  S.B. Furber,et al.  A novel area-efficient binary adder , 2000, Conference Record of the Thirty-Fourth Asilomar Conference on Signals, Systems and Computers (Cat. No.00CH37154).

[11]  Marc Snir,et al.  Depth-Size Trade-Offs for Parallel Prefix Computation , 1986, J. Algorithms.

[12]  Christian Belady.  Cooling and power consideration for semiconductors into the next century , 2001, ISLPED '01.

[13]  Cheng-Chew Lim,et al.  Parallel prefix adder design , 2001, Proceedings 15th IEEE Symposium on Computer Arithmetic. ARITH-15 2001.

[14]  Mircea R. Stan,et al.  Optimal logarithmic adder structures with a fanout of two for minimizing the area-delay product , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[15]  H. T. Kung,et al.  A Regular Layout for Parallel Adders , 1982, IEEE Transactions on Computers.

[16]  S. K. Dhall,et al.  Analysis and Design of Parallel Algorithms: Arithmetic and Matrix Problems , 1990 .

[17]  Simon Knowles,et al.  A family of adders , 1999, Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336).

[18]  Andrew G. Dempster,et al.  Using carry-save adders in low-power multiplier blocks , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[19]  Shih-Lien Lu,et al.  VLSI implementation of a 32-bit Kozen formulation Ladner/Fischer parallel prefix adder , 1995, Proceedings of Eighth International Application Specific Integrated Circuits Conference.

[20]  Kai Hwang,et al.  Computer arithmetic: Principles, architecture, and design , 1979 .

[21]  Jan M. Rabaey,et al.  Digital Integrated Circuits: A Design Perspective , 1995 .

[22]  Massoud Pedram,et al.  Low power design methodologies , 1996 .

[23]  D. Radhakrishnan,et al.  Low-voltage low-power CMOS full adder , 2001 .

[24]  R. G. Deshmukh,et al.  A novel fault-model for regular and irregular parallel-prefix adders , 1998, Proceedings IEEE Southeastcon '98 'Engineering for a New Era'.

[25]  Mary Jane Irwin,et al.  Area-time-power tradeoffs in parallel adders , 1996 .

[26]  Kaushik Roy,et al.  Low-Power CMOS VLSI Circuit Design , 2000 .

[27]  John Gehl.  Why 99.9 percent is not good enough: an interview with Peter Huber , 2000, UBIQ.

[28]  Amos R. Omondi,et al.  Computer arithmetic systems - algorithms, architecture and implementation , 1994, Prentice Hall International series in computer science.

[29]  Enrico Macii.  RT and algorithmic-level optimization for low power , 1997 .

[30]  Israel Koren.  Computer arithmetic algorithms , 1993 .

[31]  Huey Ling.  High Speed Binary Adder , 1981, IBM J. Res. Dev..

[32]  Anantha P. Chandrakasan,et al.  Low Power Digital CMOS Design , 1995 .

[33]  Uming Ko,et al.  Low-power design techniques for high-performance CMOS adders , 1995, IEEE Trans. Very Large Scale Integr. Syst..