Modeling and Fast Eye Diagram Estimation of Ringing Effects on Branch Line Structures

Significant ringing effects due to multiple reflections are first addressed for the slightly unbalanced address lines in the double data rate memory systems. A resistance-inductance-capacitance resonance model is proposed to explain its occurrence by fitting the transfer function in frequency domain. The transient analysis can then be performed easily and the peak distortion analysis is used to predict its eye height. The cases with the worst signal integrity were identified and a simple design rule is derived to avoid its occurrence, which is dependent on the attenuation constant of the transmission line and the data rate of the signal.

[1]  Wei-Da Guo,et al.  Signal/Power Integrity Modeling of High-Speed Memory Modules Using Chip-Package-Board Coanalysis , 2010, IEEE Transactions on Electromagnetic Compatibility.

[2]  Andrew B. Kahng,et al.  Mobile system considerations for SDRAM interface trends , 2011, International Workshop on System Level Interconnect Prediction.

[3]  Yong Seok Kang,et al.  Low cost DTV-SoC system implementation using integrated Signal Integrity Analysis , 2008, 2008 Asia-Pacific Symposium on Electromagnetic Compatibility and 19th International Zurich Symposium on Electromagnetic Compatibility.

[4]  Christos Christopoulos,et al.  Introduction to Electromagnetic Compatibility , 2007 .

[5]  Wenjian Yu,et al.  Accurate Eye Diagram Prediction Based on Step Response and Its Application to Low-Power Equalizer Design , 2009, IEICE Trans. Electron..

[6]  R. Mooney,et al.  An accurate and efficient analysis method for multi-Gb/s chip-to-chip signaling schemes , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

[7]  Ruey-Beei Wu,et al.  Fast Methodology for Determining Eye Diagram Characteristics of Lossy Transmission Lines , 2009, IEEE Transactions on Advanced Packaging.

[8]  Hyoungsik Nam,et al.  A 64-Mbit, 640-MByte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-MByte memory system , 1998, IEEE J. Solid State Circuits.

[9]  Stephen H. Hall,et al.  Advanced Signal Integrity for High-Speed Digital Designs , 2009 .