Characterization and Modeling of the Transient Safe Operating Area in LDMOS Transistors

The boundaries that determine the LDMOS transient safe operating area are presented. It includes the time-independent electrical SOA (eSOA) and short-pulse transient SOA post device snapback. A compact modeling methodology is introduced for high voltage LDMOS with minimal circuit simulation convergence shortcomings. By adding a failure monitor, the model proposed can be used to determine both the boundaries of eSOA and short-pulse transient SOA.

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