A novel approach to design a redundant binary signed digit adder cell using reversible logic gates

Redundant Binary Signed Digit (RBSD) number system motivates the researchers to design high speed processing devices. RBSD adders can perform fast addition of two numbers due to the phenomenon of the absence of carry calculation and manipulation requirement. This paper presents a novel approach to design RBSD adder cell using some basic reversible logic gates such as feynman, BJN and peres gate. This adder cell design can be considered as an initial work for the low loss as well as high speed digital systems. Moreover, there is scope of further optimization of various performance parameters to enhance the efficiency of the designed adder circuit. This proposed designed is simulated using Modelsim tool and synthesised for Xilinx Spartan 3E with Device XC3S500E with 200 MHz frequency.

[1]  N. Ranganathan,et al.  Design of Efficient Reversible Binary Subtractors Based on a New Reversible Gate , 2009, 2009 IEEE Computer Society Annual Symposium on VLSI.

[2]  Vandana Shukla,et al.  Design of a 4-bit 2's Complement Reversible Circuit for Arithmetic Logic Unit Applications , 2013 .

[3]  Lavanya Thunuguntla,et al.  Designing of Efficient Online Testable Reversible Multiplexers and DeMultiplexers with New Reversible Gate , 2012 .

[4]  N. Ranganathan,et al.  A novel optimization method for reversible logic circuit minimization , 2013, 2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

[5]  Himanshu Thapliyal,et al.  A New Reversible TSG Gate and Its Application For Designing Efficient Adder Circuits , 2006, ArXiv.

[6]  A. V. N. Tilak,et al.  Reversible Arithmetic Logic Unit , 2011, 2011 3rd International Conference on Electronics Computer Technology.

[7]  R. Feynman.  Quantum mechanical computers , 1986 .

[8]  Mitchell A. Thornton,et al.  Efficient adder circuits based on a conservative reversible logic gate , 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.

[9]  Goutam Sanyal,et al.  HMM based Offline Handwritten Writer Independent English Character Recognition using Global and Local Feature Extraction , 2012 .

[10]  Charles H. Bennett,et al.  Logical reversibility of computation , 1973 .

[11]  Michael P. Frank,et al.  Introduction to reversible computing: motivation, progress, and challenges , 2005, CF '05.

[12]  A. G. Rao,et al.  Design of low power comparator circuit based on reversible logic technology , 2013, 2013 1st International Conference on Emerging Trends and Applications in Computer Science.

[13]  A. K. Wadhwani,et al.  Fast Adder Design using Redundant Binary Numbers with Reduced Chip Complexity , 2011 .

[14]  R Chinmaye,et al.  Design, Optimization and Synthesis of Efficient Reversible Logic Binary Decoder , 2012 .

[15]  Behrooz Parhami,et al.  Carry-Free Addition of Recorded Binary Signed-Digit Numbers , 1988, IEEE Trans. Computers.

[16]  T. N. Rajashekhara,et al.  Fast multiplier design using redundant signed-digit numbers , 1990 .

[17]  Algirdas Avizienis,et al.  Signed-Digit Numbe Representations for Fast Parallel Arithmetic , 1961, IRE Trans. Electron. Comput..

[18]  Tommaso Toffoli,et al.  Reversible Computing , 1980, ICALP.

[19]  Keivan Navi,et al.  A Novel Fault Tolerant Reversible Gate For Nanotechnology Based Systems , 2008 .

[20]  Wenjuan Li,et al.  Using new designed NLG gate for the realization of four-bit reversible numerical comparator , 2010, 2010 International Conference on Educational and Network Technology.

[21]  Keivan Navi,et al.  A Novel Reversible Full Adder Circuit for Nanotechnology Based Systems , 2007 .

[22]  Dhananjay S. Phatak,et al.  Hybrid Signed-Digit Number Systems: A Unified Framework for Redundant Number Representations With Bounded Carry Propagation Chains , 1994, IEEE Trans. Computers.

[23]  Vandana Shukla,et al.  A novel approach to design decimal to BCD encoder with reversible logic , 2014, 2014 International Conference on Power, Control and Embedded Systems (ICPCES).

[24]  Atal Chaudhuri,et al.  Realization of a Novel Reversible SCG Gate and its Application for Designing Parallel Adder/Subtractor and Match Logic , 2011 .

[25]  T. Toffoli,et al.  Conservative logic , 2002, Collision-Based Computing.

[26]  Pérès,et al.  Reversible logic and quantum computers. , 1985, Physical review. A, General physics.

[27]  Majid Haghparast,et al.  On the Synthesis of Different Nanometric Reversible Converters , 2011 .

[28]  G.E. Moore,et al.  Cramming More Components Onto Integrated Circuits , 1998, Proceedings of the IEEE.

[29]  Rolf Landauer,et al.  Irreversibility and heat generation in the computing process , 1961, IBM J. Res. Dev..