High-Level Combined Deterministic and Pseudo-exhuastive Test Generation for RISC Processors

Recent safety standards set stringent requirements for the target fault coverage in embedded microprocessors, with the objective to guarantee robustness and functional safety of the critical electronic systems. This motivates the need for improving the quality of test generation for microprocessors. A new high-level implementation-independent test generation method for RISC processors is proposed. The set of instructions of the processor is partitioned into groups. For each group, a dedicated test template is created, to be used for generating two test programs, for testing the control and the data paths respectively. For testing the control part, a novel high-level control fault model is proposed. Using this model, a set of deterministic test data operands are generated for each instruction of the given group. The advantage of the high-level fault model is that it covers larger than SAF fault class including multiple fault coverage in the control part. For generating the data path test, pseudo-exhaustive data operands are used. We investigated the feasibility of the approach and demonstrated high efficiency of the generated test programs for testing the execute module of the miniMIPS RISC processor.

[1]  Bernd Becker,et al.  A Flexible Framework for the Automatic Generation of SBST Programs , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Paolo Bernardi,et al.  On the Functional Test of the Register Forwarding and Pipeline Interlocking Unit in Pipelined Processors , 2013, 2013 14th International Workshop on Microprocessor Test and Verification.

[3]  Mariagrazia Graziano,et al.  On the functional test of the BTB logic in pipelined and superscalar processors , 2013, 2013 14th Latin American Test Workshop - LATW.

[4]  Douglas B. Armstrong,et al.  On Finding a Nearly Minimal Set of Fault Detection Tests for Combinational Logic Nets , 1966, IEEE Trans. Electron. Comput..

[5]  Srivaths Ravi,et al.  Systematic Software-Based Self-Test for Pipelined Processors , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[6]  Paolo Bernardi,et al.  Development Flow for On-Line Core Self-Test of Automotive Microcontrollers , 2016, IEEE Transactions on Computers.

[7]  Jian Shen,et al.  Native mode functional test generation for processors with applications to self test and design validation , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[8]  Heinrich Theodor Vierhaus,et al.  Towards an automatic generation of diagnostic in-field SBST for processor components , 2013, 2013 14th Latin American Test Workshop - LATW.

[9]  Michail Maniatakos,et al.  Systematic Software-Based Self-Test for Pipelined Processors , 2008, IEEE Trans. Very Large Scale Integr. Syst..

[10]  Kwang-Ting Cheng,et al.  Simulation-Based Functional Test Generation for Embedded Processors , 2006, IEEE Transactions on Computers.

[11]  Matteo Sonza Reorda,et al.  On the functional test of the cache coherency logic in multi-core systems , 2015, 2015 IEEE 6th Latin American Symposium on Circuits & Systems (LASCAS).

[12]  Jacob A. Abraham,et al.  Automatic generation of instruction sequences targeting hard-to-detect structural faults in a processor , 2006, 2006 IEEE International Test Conference.

[13]  Hans-Joachim Wunderlich,et al.  Adaptive Debug and Diagnosis without Fault Dictionaries , 2007, ETS.

[14]  Niraj K. Jha,et al.  Satisfiability-Based Automatic Test Program Generation and Design for Testability for Microprocessors , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[15]  Giovanni Squillero,et al.  Automatic test program generation: a case study , 2004, IEEE Design & Test of Computers.

[16]  William Lindsay,et al.  FRITS - a microprocessor functional BIST method , 2002, Proceedings. International Test Conference.

[17]  Ismet Bayraktaroglu,et al.  Cache Resident Functional Microprocessor Testing: Avoiding High Speed IO Issues , 2006, 2006 IEEE International Test Conference.

[18]  John P. Hayes,et al.  On the properties of the input pattern fault model , 2003, TODE.

[19]  Alessandro Savino,et al.  Software-Based Self-Test of Set-Associative Cache Memories , 2011, IEEE Transactions on Computers.

[20]  Sujit Dey,et al.  Software-based self-testing methodology for processor cores , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[21]  Chung-Ho Chen,et al.  Software-Based Self-Testing With Multiple-Level Abstractions for Soft Processor Cores , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[22]  Matteo Sonza Reorda,et al.  On the Functional Test of Branch Prediction Units , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[23]  Giovanni Squillero,et al.  Rejuvenation of NBTI-Impacted Processors Using Evolutionary Generation of Assembler Programs , 2016, 2016 IEEE 25th Asian Test Symposium (ATS).

[24]  Dimitris Gizopoulos,et al.  Software-based self-testing of embedded processors , 2005, IEEE Transactions on Computers.

[25]  Paolo Bernardi,et al.  On the in-field functional testing of decode units in pipelined RISC processors , 2014, 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

[26]  Raimund Ubar,et al.  Parallel Pseudo-Exhaustive Testing of Array Multipliers with Data-Controlled Segmentation , 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

[27]  Raimund Ubar,et al.  High-level test data generation for software-based self-test in microprocessors , 2017, 2017 6th Mediterranean Conference on Embedded Computing (MECO).