High-level circuit modeling for power estimation

In this paper, a method for accurate modeling of timing behavior and power consumption of digital circuits is presented. The model is based on the parameter extraction of the basic cells by circuit level simulations. This information is then embedded in a high-level description (VHDL) for every basic cell. The circuit simulations for each cell are executed only once in order to create a cell library including the VHDL models. Due to the complex timing model in the high-level descriptions, the switching activity in a larger circuit can be determined quite accurately. Besides timing, the power consumption for every possible input transition is also included in the cell descriptions. Thus, quite accurate power estimation of large circuits is possible by a simple event driven simulation with a conventional VHDL-simulator. The computation time of this method is about four orders of magnitude shorter than power estimation by SPICE. The presented model in combination with the VHDL-simulator is applied for the comparing different multiplier architectures in terms of power consumption.