A 3.3 V 350 MHz 0.35 µm CMOS programmable RIF based on redundant coding in a bit plane architecture

A 350 MHz programmable RIF was realised. This filter is used as a basic circuit in a terrestrial 622 Mbit/s ATM distribution system. In addition to the filtering function, multiplication, addition, saturation and inversions at the same 350 MHz clock rate frequency are processed. The technological process is five-metal 3.3 V 0.35 μm CMOS.

[1]  Tobias G. Noll Carry-save architectures for high-speed digital signal processing , 1991, J. VLSI Signal Process..

[2]  Patrice Senn,et al.  A Compiled 100 MHz Programmable FIR Filter Chip for Data Acquisition , 1994, ESSCIRC '94: Twientieth European Solid-State Circuits Conference.