Symbolic Petri Net Analysis Using Boolean Manipulation

This work presents an ennumerative analysis approach for bounded Petri nets. The structure and behavior of the petri net are symbolically modeled by using boolean functions; thus, reducing reasoning about Petri nets to boolean calculation. The set of reachable markings is enumerated by symbolically ring the transitions in the Petri net. Highly concurrent Petri nets may suuer from the state explosion problem; that is, an exponential increase in the number of reachable markings. This state explosion is managed by using Binary Decision Diagrams (BDDs), which are capable to represent large sets of markings in small data structures. Petri nets have the ability to model a large variety of systems, the exibility to describe causality, concurrency and conditional relations. These inherent features, together with the generality of boolean algebras, and the eecient implementation of BDDs, provide a general environment to eeciently analyze a wide range of problems, e.g. deadlock freeness, liveness, concurrency. A number of examples are presented in order to show how large reachability sets (up to 10 18 markings) generated, represented, and analyzed with moderate BDD sizes (only 10 3 nodes). By using this symbolic framework, properties requiring an exhaustive analysis of the reachability graph can be veriied in polynomial time with respect to the size of the BDD. 1 Petri nets are a graph based mathematical formalism adequate to describe, model and analyze the behavior of discrete event concurrent systems. More precisely, they allow the description of asynchronous sequential and non-sequential behaviors (including concurrence and nondeterministic choice), where sets of processes can interact, cooperate and compete. Since its introduction by C.A.Petri in 1962 21], Petri nets (PNs) have been extensively used in a wide range of areas such as communication protocols and networks, computer architecture, distributed systems, manufacturing planning, digital circuit synthesis and veriication, and high-level synthesis. In particular, they play an increasingly important role in the synthesis and veriication of digital asynchronous circuits 23, 11, 7]. Several methods for the analysis of PNs have been proposed in the literature. They can be mainly classiied into four categories 18], reachability tree methods, enumerative methods, matrix-equation methods, and reduction or decomposition methods. Traditionally, the rst and second methods are only applicable to small PNs due to the explosion of the number of markings, while the third and forth methods are restricted to special sub-classes of nets. Enumerative methods permit to answer of any analysis question in systems with a …

[1]  Olivier Coudert,et al.  Formal Boolean manipulations for the verification of sequential machines , 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

[2]  Alexandre Yakovlev,et al.  Checking signal transition graph implementability by symbolic BDD traversal , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[3]  Edmund M. Clarke,et al.  Symbolic Model Checking: 10^20 States and Beyond , 1990, Inf. Comput..

[4]  Jordi Cortadella,et al.  Verification of Asynchronous Circuits by BDD-based Model Checking of Petri Nets , 1995, Application and Theory of Petri Nets.

[5]  Frank M. Brown,et al.  Boolean reasoning - the logic of boolean equations , 1990 .

[6]  C. Petri.  Kommunikation mit Automaten , 1962 .

[7]  Tadao Murata,et al.  Petri nets: Properties, analysis and applications , 1989, Proc. IEEE.

[8]  Chen-Shang Lin,et al.  On the OBDD-Representation of General Boolean Functions , 1992, IEEE Trans. Computers.

[9]  Tam-Anh Chu,et al.  Synthesis of self-timed VLSI circuits from graph-theoretic specifications , 1987 .

[10]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[11]  Luciano Lavagno,et al.  Algorithms for synthesis of hazard-free asynchronous circuits , 1991, 28th ACM/IEEE Design Automation Conference.

[12]  Randal E. Bryant,et al.  Efficient implementation of a BDD package , 1991, DAC '90.

[13]  Jordi Cortadella,et al.  Structural methods for the synthesis of speed-independent circuits , 1996, Proceedings ED&TC European Design and Test Conference.

[14]  Jordi Cortadella,et al.  Petri Net Analysis Using Boolean Manipulation , 1994, Application and Theory of Petri Nets.

[15]  Kenneth L. McMillan,et al.  Using Unfoldings to Avoid the State Explosion Problem in the Verification of Asynchronous Circuits , 1992, CAV.

[16]  Jörg Desel,et al.  Free choice Petri nets , 1995 .

[17]  C. Y. Lee.  Representation of switching circuits by binary-decision programs , 1959 .

[18]  Alexandre Yakovlev,et al.  Signal Graphs: From Self-Timed to Timed Ones , 1985, PNPM.

[19]  Robert K. Brayton,et al.  Implicit state enumeration of finite state machines using BDD's , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[20]  Luciano Lavagno,et al.  Synthesizing Petri nets from state-based models , 1995, ICCAD.

[21]  Robert K. Brayton,et al.  On Computing the Transitive Closure of a State Transition Relation , 1993, 30th ACM/IEEE Design Automation Conference.

[22]  Wolfgang Reisig.  Petri Nets: An Introduction , 1985, EATCS Monographs on Theoretical Computer Science.

[23]  Jerry R. Burch.  Verifying Liveness Properties by Verifying Safety Properties , 1990, CAV.