论文信息 - Ultra High Speed CNFET Full-Adder Cell Based on Majority Gates

Ultra High Speed CNFET Full-Adder Cell Based on Majority Gates

In this paper an ultra high speed CNFET Full-Adder cell is presented. This design generates sum and carry-out signals via majority and majority-not gates which are implemented by CNFET buffer, CNFET inverter and input capacitors. Significant improvement in terms of speed and Power-Delay Product (PDP) is achieved.

[1] Jie Deng,et al. A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application—Part II: Full Device Model and Circuit Performance Benchmarking , 2007, IEEE Transactions on Electron Devices.

[2] Phaedon Avouris. Carbon nanotube electronics , 2002 .

[3] J. Chen,et al. Optical properties of the semiconductor carbon nanotube intramolecular junctions , 2004 .

[4] Keivan Navi,et al. Two novel ultra high speed carbon nanotube Full-Adder cells , 2009, IEICE Electron. Express.

[5] Chip-Hong Chang,et al. A review of 0.18-/spl mu/m full adder performances for tree structured arithmetic circuits , 2005 .

[6] Bin Liu,et al. A molecular mechanics approach for analyzing tensile nonlinear deformation behavior of single-walled carbon nanotubes , 2007 .

[7] Min-Feng Yu,et al. Fundamental Mechanical Properties of Carbon Nanotubes: Current Understanding and the Related Experimental Studies , 2004 .

[8] Keivan Navi,et al. Two new low-power Full Adders based on majority-not gates , 2009, Microelectron. J..

[9] Keivan Navi,et al. Universal ternary logic circuit design through carbon nanotube technology , 2009 .