A hardware efficient control of memory addressing for high-performance FFT processors

The conventional memory organization of fast Fourier transform (FFT) processors is based on Cohen's (1976) scheme. Compared with this scheme, our scheme reduces the hardware complexity of address generation by about 50% while improving the memory access speed. Much power consumption in memory is saved since only half of the memory is activated during memory access, and the number of coefficient access is reduced to a minimum by using a new ordering of FFT butterflies. Therefore, the new scheme is a superior solution to constructing high-performance FFT processors.

[1]  Yu Tai Ma,et al.  A VLSI-oriented parallel FFT algorithm , 1996, IEEE Trans. Signal Process..

[2]  Lewis Johnson,et al.  Conflict free memory addressing for dedicated FFT hardware , 1992 .

[3]  Bevan M. Baas.  A 9.5 mW 330 /spl mu/sec 1024-point FFT processor , 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

[4]  Marshall C. Pease,et al.  Organization of Large Scale Fourier Processors , 1969, J. ACM.

[5]  Bevan M. Baas.  A 9.5mW 330psec 1024-point FFT Processor , 1998 .

[6]  C. Joanblanq,et al.  A fast single-chip implementation of 8192 complex point FFT , 1995 .

[7]  B.M. Baas.  An energy-efficient single-chip FFT processor , 1996, 1996 Symposium on VLSI Circuits. Digest of Technical Papers.

[8]  Lars Wanhammar.  DSP integrated circuits , 1999 .

[9]  D. Cohen.  Simplified control of FFT hardware , 1976 .

[10]  Yutai Ma,et al.  An effective memory addressing scheme for FFT processors , 1999, IEEE Trans. Signal Process..