New code construction method and high-speed VLSI codec architecture for repeat-accumulate codes

Repeat-Accumulate code has been widely used in various practical communication systems due to its special structure that can be encoded with a low complexity turbo-like encoder and decoded with a high-speed parallel algorithm. However, the construction of RA codes with large girth is still a challenging problem. In this paper, the girth upper bound of RA codes is analyzed and a novel RA code construction scheme is proposed. This scheme generates the parity-check matrix with superimposed structured interleavers, guaranteeing the resulting matrix to be globally optimized. Compared with the RA codes constructed with traditional structured interleavers such as π-rotation interleavers, pseudo-random interleavers, combinatorial interleavers, and modified L-type interleavers, the codes constructed with the proposed method exhibit better error-correcting performance. Moreover, a parallel VLSI codec architecture is proposed for the RA codes generated with the proposed method in this paper. Modifying the conventional RA encoder architecture, the codec for RA codes from our proposed method may have the same hardware implementation complexity as that for traditional RA codes, while the data throughput of our codec may achieve up to 450Mbps, which may be of great value for practical applications.

[1]  Sarah J. Johnson,et al.  Practical Interleavers for Systematic Repeat-Accumulate Codes , 2006, 2006 IEEE 63rd Vehicular Technology Conference.

[2]  William E. Ryan,et al.  Design of efficiently encodable moderate-length high-rate irregular LDPC codes , 2004, IEEE Transactions on Communications.

[3]  Jianhua Lu,et al.  Design of irregular LDPC codec on a single chip FPGA , 2004, Proceedings of the IEEE 6th Circuits and Systems Symposium on Emerging Technologies: Frontiers of Mobile and Wireless Communication (IEEE Cat. No.04EX710).

[4]  T. Etzion,et al.  Which codes have cycle-free Tanner graphs? , 1998, Proceedings. 1998 IEEE International Symposium on Information Theory (Cat. No.98CH36252).

[5]  Sae-Young Chung,et al.  On the design of low-density parity-check codes within 0.0045 dB of the Shannon limit , 2001, IEEE Communications Letters.

[6]  Zhongfeng Wang,et al.  A memory efficient FPGA implementation of quasi-cyclic LDPC decoder , 2006 .

[7]  Sarah J. Johnson,et al.  Combinatorial Interleavers for Systematic Regular Repeat-Accumulate Codes [Transactions Letters] , 2008, IEEE Transactions on Communications.

[8]  A. Glavieux,et al.  Near Shannon limit error-correcting coding and decoding: Turbo-codes. 1 , 1993, Proceedings of ICC '93 - IEEE International Conference on Communications.

[9]  J. Thorpe.  Low-Density Parity-Check (LDPC) Codes Constructed from Protographs , 2003 .

[10]  Robert G. Gallager,et al.  Low-density parity-check codes , 1962, IRE Trans. Inf. Theory.

[11]  Alberto Morello,et al.  DVB-S2: The Second Generation Standard for Satellite Broad-Band Services , 2006, Proceedings of the IEEE.

[12]  Mohammed Nafie,et al.  On the Enhancement of LDPC Codes in the IEEE 802.16 Physical Layer , 2007, 2007 IEEE International Conference on Communications.

[13]  Jung-Fu Cheng,et al.  Turbo Decoding as an Instance of Pearl's "Belief Propagation" Algorithm , 1998, IEEE J. Sel. Areas Commun..

[14]  Shih-Chun Chang,et al.  The /spl pi/-rotation low-density parity check codes , 2001, GLOBECOM'01. IEEE Global Telecommunications Conference (Cat. No.01CH37270).

[15]  Xin-Yu Shih,et al.  A 19-mode 8.29mm2 52-mW LDPC Decoder Chipp for IEEE 802.16e System , 2007, 2007 IEEE Symposium on VLSI Circuits.

[16]  Dariush Divsalar,et al.  Coding theorems for 'turbo-like' codes , 1998 .

[17]  Rüdiger L. Urbanke,et al.  Design of capacity-approaching irregular low-density parity-check codes , 2001, IEEE Trans. Inf. Theory.