Simulating a LAGS processor to consider variable latency on L1 D-Cache

Variability is one of the important issues in deep-submicron tecnologies, and the assumption of non-variable, constant latencies in the modules of deep-submicron processors can jeopardize their performance. Cache memories have demonstrated their data-dependent latency due to factors like the coupling capacitances or the distance between the port and the required data. In this paper we present, on one hand, a scheme to detect read operation completion on a variable latency cache memory. On the other hand, we present an asynchronous approach to improve processor performance using this feature. Hence, we propose a Locally-Asynchronous Globally-Synchronous (LAGS) superscalar microarchitecture in which read operations on a variable latency L1 data cache are managed through an asynchronous wrapper. In addition, we demonstrate its feasibility running SPEC2000 benchmarks on a 64-bit superscalar processor modeled through an architectural simulator. Simulations show speedups ranging up to 1.44 and averaging 1.22 over a non-variable cache design.

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