A survey on binary decision diagram approaches to symbolic analysis of analog integrated circuits

Applying symbolic techniques for analog circuit analysis is a traditional research subject, which has lasted for over half a century. The past decade has witnessed a significant advancement of the symbolic techniques developed specifically for large analog integrated circuits. The key methodology introduced is a data structure called binary decision diagram (BDD) which was established originally for logic design and verification. The application of the BDD technique for analog circuit analysis has the following features: (1) It is a compact data structure so that data redundancy in symbolic analysis can be eliminated. (2) It provides a mechanism for implicit enumeration method so that exhaustive enumeration commonly performed in symbolic analysis can be avoided. (3) Numerical evaluation on a BDD can be made extremely efficient, making it an excellent means for repetitive analysis. More advanced features are yet to be explored. This survey brings together the significant research results published in the past decade and provides a tutorial overview on the basic principles of applying BDD to analog circuit analysis. Some new directions that are potentially valuable for developing future analog design automation tools are discussed and a design example is given to illustrate the application of symbolic techniques.

[1]  Weiwei Chen,et al.  Implementation of a Symbolic Circuit Simulator for Topological Network Analysis , 2006, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems.

[2]  Ranga Vemuri,et al.  A regularity-based hierarchical symbolic analysis method for large-scale analog networks , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[3]  Sheldon X.-D. Tan,et al.  Hierarchical approach to exact symbolic analysis of large analog circuits , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Kishore Singhal,et al.  Computer Methods for Circuit Analysis and Design , 1983 .

[5]  Huiying Yang,et al.  Efficient symbolic sensitivity analysis of analog circuits using element-coefficient diagrams , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[6]  O. Guerra,et al.  Approximate Symbolic Analysis of Hierarchically Decomposed Analog Circuits , 2002 .

[7]  Ronald A. Rohrer,et al.  Pole and zero sensitivity calculation in asymptotic waveform evaluation , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Guoyong Shi,et al.  Variational analog integrated circuit design via symbolic sensitivity analysis , 2009, 2009 IEEE International Symposium on Circuits and Systems.

[9]  Shin-ichi Minato,et al.  Zero-Suppressed BDDs for Set Manipulation in Combinatorial Problems , 1993, 30th ACM/IEEE Design Automation Conference.

[10]  P. Lin.  Symbolic network analysis , 1991 .

[11]  Sheldon X.-D. Tan.  A general hierarchical circuit modeling and simulation algorithm , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[12]  C.-J. Richard Shi,et al.  A Graph Reduction Approach to Symbolic Circuit Analysis , 2007, 2007 Asia and South Pacific Design Automation Conference.

[13]  Georges Gielen,et al.  Efficient DDD-based symbolic analysis of linear analog circuits , 2002 .

[14]  Randal E. Bryant,et al.  Formal Methods for Functional Verification , 2003 .

[15]  Sofia Cassel,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 2012 .

[16]  A. Rodríguez-Vázquez,et al.  A Symbolic Pole/Zero Extraction Methodology Based on Analysis of Circuit Time-Constants , 2002 .

[17]  Kong-Pang Pun,et al.  Reversed nested Miller compensation with voltage buffer and nulling resistor , 2003, IEEE J. Solid State Circuits.

[18]  S. Minato.  Binary Decision Diagrams and Applications for VLSI CAD , 1995 .

[19]  Ranga Vemuri,et al.  Fast analog circuit synthesis using multiparameter sensitivity analysis based on element-coefficient diagrams , 2005, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05).

[20]  Guoyong Shi.  A simple implementation of determinant decision diagram , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[21]  Randal E. Bryant,et al.  Efficient implementation of a BDD package , 1991, DAC '90.

[22]  Guoyong Shi.  Computational Complexity Analysis of Determinant Decision Diagram , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

[23]  Hui Xu,et al.  Hierarchical symbolic sensitivity computation with applications to large amplifier circuit design , 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

[24]  Vinita Vasudevan,et al.  Symbolic analysis of analog integrated circuits , 1998, Proceedings Eleventh International Conference on VLSI Design.

[25]  P.R. Gray,et al.  MOS operational amplifier design-a tutorial overview , 1982, IEEE Journal of Solid-State Circuits.

[26]  G. Minty,et al.  A Simple Algorithm for Listing All the Trees of a Graph , 1965 .

[27]  Guoyong Shi,et al.  A design platform for analog device size sensitivity analysis and visualization , 2010, 2010 IEEE Asia Pacific Conference on Circuits and Systems.

[28]  Georges Gielen,et al.  Symbolic analysis methods and applications for analog circuits: a tutorial overview , 1994, Proc. IEEE.

[29]  Sheldon X.-D. Tan,et al.  Compact representation and efficient generation of s-expandedsymbolic network functions for computer-aided analog circuit design , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[30]  Rob A. Rutenbar,et al.  Canonical Symbolic Analysis of Large Analog Circuits with Determinant Decision Diagrams , 2002 .

[31]  Albert E. Ruehli,et al.  The modified nodal approach to network analysis , 1975 .

[32]  Sheldon X.-D. Tan,et al.  Hierarchical symbolic analysis of analog integrated circuits viadeterminant decision diagrams , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[33]  G. Nebel,et al.  Symbolic Pole/Zero Calculation using SANTAFE , 1994, ESSCIRC '94: Twientieth European Solid-State Circuits Conference.

[34]  Hui Xu,et al.  Hierarchical exact symbolic analysis of large analog integrated circuits by symbolic stamps , 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

[35]  Georges Gielen,et al.  Symbolic analysis for automated design of analog integrated circuits , 1991, The Kluwer international series in engineering and computer science.

[36]  Sheldon X.-D. Tan.  Symbolic Analysis of Analog Circuits By Boolean Logic Operations , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

[37]  Sheldon X.-D. Tan,et al.  Efficient approximation of symbolic expressions for analog behavioral modeling and analysis , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[38]  Qicheng Yu,et al.  A unified approach to the approximate symbolic analysis of large analog integrated circuits , 1996 .