Encoding-based minimization of inductive cross-talk for off-chip data transmission

Inductive cross-talk within IC packaging is becoming a significant bottleneck in high-speed inter-chip communication. The parasitic inductance within IC packaging causes bounce on the power supply pins in addition to glitches and rise-time degradation on the signal pins. Until recently, the parasitic inductance problem was addressed by aggressive package design. We present a technique to encode the off-chip data transmission to limit bounce on the supplies and reduce inductive signal coupling due to transitions on neighboring signal lines. Both these performance limiting factors are modeled in a common mathematical framework. Our experimental results show that the proposed encoding based techniques result in reduced supply bounce and signal degradation due to inductive cross-talk, closely matching the theoretical predictions. We demonstrate that the overall bandwidth of a bus actually increases by 85% using our technique, even after accounting for the encoding overhead. The asymptotic bus size overhead is between 30% and 50%, depending on how stringent the user-specified inductive cross-talk parameters are.

[1]  F. Sandoval-Ibarra,et al.  Design of CMOS buffers using the settling time of the ground bounce voltage as a key parameter , 2000, Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144).

[2]  Chunjie Duan,et al.  Exploiting crosstalk to speed up on-chip buses , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[3]  Kurt Keutzer,et al.  Bus encoding to prevent crosstalk delay , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[4]  W. Arden The International Technology Roadmap for Semiconductors—Perspectives and challenges for the next 15 years , 2002 .

[5]  C. L. Chen,et al.  Switching Codes for Delta-I Noise Reduction , 1996, IEEE Trans. Computers.

[6]  J. L. Prince,et al.  Influence of a floating plane on effective ground plane inductance in multilayer and coplanar packages , 1999, ECTC 1999.

[7]  T. Sudo,et al.  Electrical characterization and modeling of simultaneous switching noise for leadframe packages , 1995, 1995 Proceedings. 45th Electronic Components and Technology Conference.

[8]  T. Sudo,et al.  Characterization and reduction of simultaneous switching noise for a multilayer package , 1994, 1994 Proceedings. 44th Electronic Components and Technology Conference.

[9]  T. N. Vijaykumar,et al.  Pipeline damping: a microarchitectural technique to reduce inductive noise in supply voltage , 2003, ISCA '03.

[10]  Chunjie Duan,et al.  Analysis and avoidance of cross-talk in on-chip buses , 2001, HOT 9 Interconnects. Symposium on High Performance Interconnects.

[11]  B. Young Return path inductance in measurements of package inductance matrixes , 1997 .