Design, fabrication, and calibration of stress sensors embedded in a TSV interposer in a 300mm wafer

In this study, the design, fabrication, and calibration of the piezoresistive stress sensors [1-18] embedded in a TSV (through silicon via) interposer in a 300mm wafer are investigated. The results presented herein should be useful for the development of 3D integration such as measuring the strength of the TSV device and interposer wafers, during and after all the processes such as wafer thinning, SiO2 deposition, metallization, and electroplating.

[1]  H. Miura,et al.  Structural effect of IC plastic package on residual stress in silicon chips , 1990, 40th Conference Proceedings on Electronic Components and Technology.

[2]  James N. Sweet,et al.  Die Stress Measurement Using Piezoresistive Stress Sensors , 1993 .

[3]  Seung Wook Yoon,et al.  Development of Super Thin TSV PoP , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[4]  Qing Xin Zhang,et al.  Application of piezoresistive stress sensors in ultra thin device handling and characterization , 2009 .

[5]  K. Zoschke,et al.  3D image sensor SiP with TSV silicon interposer , 2009, 2009 59th Electronic Components and Technology Conference.

[6]  Darvin R. Edwards,et al.  Shear Stress Evaluation of Plastic Packages , 1987 .

[7]  Residual Stress Analysis in Thin Device Wafer Using Piezoresistive Stress Sensor , 2011, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[8]  A. Kumar,et al.  Evaluation of Stresses in Thin Device Wafer using Piezoresistive Stress Sensor , 2008, 2008 10th Electronics Packaging Technology Conference.

[9]  R. Jaeger,et al.  Wafer-level calibration of stress sensing test chips , 1994, 1994 Proceedings. 44th Electronic Components and Technology Conference.

[10]  Heng-Chieh Chien,et al.  Thermal evaluation and analyses of 3D IC integration SiP with TSVs for network system applications , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[11]  M. Brillhart,et al.  Addressing bandwidth challenges in next generation high performance network systems with 3D IC integration , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[12]  S. A. Gee,et al.  The Design And Calibration Of A Semiconductor Strain Gauge Array , 1988, Proceedings of the IEEE International Conference on Microelectronic Test Structures.

[13]  John H. Lau,et al.  Development of through silicon via (TSV) interposer technology for large die (21×21mm) fine-pitch Cu/low-k FCBGA package , 2009, 2009 59th Electronic Components and Technology Conference.

[14]  G. Mori,et al.  Through-silicon-via technology for 3D integration , 2010, 2010 IEEE International Memory Workshop.

[15]  Dongwook Kim,et al.  Interposer design optimization for high frequency signal transmission in passive and active interposer using through silicon via (TSV) , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[16]  Richard C. Jaeger,et al.  Piezoresistive Stress Sensors for Structural Analysis of Electronic Packages , 1991 .

[17]  F. Waldron,et al.  Sources of variation in piezoresistive stress sensor measurements , 2004, IEEE Transactions on Components and Packaging Technologies.

[18]  John H. Lau,et al.  Three dimensional interconnects with high aspect ratio TSVs and fine pitch solder microbumps , 2009, 2009 59th Electronic Components and Technology Conference.

[19]  D. Pinjala,et al.  Fabrication of Silicon Carriers With TSV Electrical Interconnections and Embedded Thermal Solutions for High Power 3-D Packages , 2009, IEEE Transactions on Components and Packaging Technologies.

[20]  H. Reichl,et al.  3D integration of image sensor SiP using TSV silicon interposer , 2009, 2009 11th Electronics Packaging Technology Conference.

[21]  C. Selvanayagam,et al.  Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip Microbumps , 2009, IEEE Transactions on Advanced Packaging.

[22]  R.C. Jaeger,et al.  Silicon piezoresistive stress sensors and their application in electronic packaging , 2001, IEEE Sensors Journal.

[23]  Richard C. Jaeger,et al.  Evaluation of piezoresistive coefficient variation in silicon stress sensors using a four-point bending test fixture , 1992 .

[24]  Kuo-Shu Kao,et al.  Assembly process and reliability assessment of TSV/RDL/IPD interposer with multi-chip-stacking for 3D IC integration SiP , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[25]  K. Y. Au,et al.  3D chip stacking & reliability using TSV-micro C4 solder interconnection , 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).

[26]  Sheng-Tsai Wu,et al.  Feasibility Study of a 3D IC Integration System-in-Packaging (SiP) from a 300mm Multi-Project Wafer (MPW) , 2011 .

[27]  Lars Brusberg,et al.  Glass panel processing for electrical and optical packaging , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[28]  M. Sunohara,et al.  Studies on electrical performance and thermal stress of a silicon interposer with TSVs , 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).

[29]  Christian Baks,et al.  Terabit/sec-class board-level optical interconnects through polymer waveguides using 24-channel bidirectional transceiver modules , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[30]  D. Kwong,et al.  Application of piezoresistive stress sensor in wafer bumping and drop impact test of embedded ultra thin device , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[31]  Zhaowei Zhong,et al.  Calibration of a piezoresistive stress sensor in [100] silicon test chips , 2002, 4th Electronics Packaging Technology Conference, 2002..

[32]  P. Lall,et al.  Die stress characterization in flip chip on laminate assemblies , 2005, IEEE Transactions on Components and Packaging Technologies.

[33]  B. Banijamali,et al.  Advanced reliability study of TSV interposers and interconnects for the 28nm technology FPGA , 2011, Electronic Components and Technology Conference.

[34]  W. Landers,et al.  3D copper TSV integration, testing and reliability , 2011, 2011 International Electron Devices Meeting.

[35]  P.C.H. Chan,et al.  Design and calibration of a 3-D micro-strain gauge for in situ on chip stress measurements , 1996, ICSE '96. 1996 IEEE International Conference on Semiconductor Electronics. Proceedings.

[36]  H. Noma,et al.  IMC bonding for 3D interconnection , 2010, 2010 Proceedings 60th Electronic Components and Technology Conference (ECTC).

[37]  Young-Hyun Jun,et al.  8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology , 2009, IEEE Journal of Solid-State Circuits.