10–315-MHz Cascaded Hybrid Phase-Locked Loop for Pixel Clock Generation

A cascaded hybrid phase-locked loop (PLL) fabricated in a 65-nm CMOS process consumes 21 mW and occupies 0.4 mm2. An all-digital PLL (ADPLL) with piecewise linear calibrated hierarchical time-to-digital converter is proposed to achieve a wide operation range, and a charge-pump PLL (CPPLL) with an auxiliary (AUX) charge-pump for low current mismatch is cascaded to filter out the ADPLL output noise. The ADPLL achieves low long-term jitter regardless of the leakage current, and the CPPLL realizes low short-term jitter using a self-biased technique and the AUX charge pump. A phase-selectable divider is also proposed to divide the clock frequency while keeping the relative phase difference constant. The measured peak-to-peak short-term and long-term jitters at an output frequency of 315 MHz are 40 and 70 pspp, respectively, with a multiplication factor of 1024.

[1]  Poras T. Balsara,et al.  Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process , 2003, IEEE Trans. Circuits Syst. II Express Briefs.

[2]  Ching-Che Chung,et al.  A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications , 2006 .

[3]  F. Gardner,et al.  Charge-Pump Phase-Lock Loops , 1980, IEEE Trans. Commun..

[4]  Deog-Kyoon Jeong,et al.  A PVT-Tolerant Low-1/f Noise Dual-Loop Hybrid PLL in 0.18/spl mu/m , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[5]  Salvatore Levantino,et al.  Quantization Effects in All-Digital Phase-Locked Loops , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

[6]  Behzad Razavi.  Phase-locking in wireline systems: Present and future , 2008, 2008 IEEE Custom Integrated Circuits Conference.

[7]  Chih-Kong Ken Yang,et al.  Jitter optimization based on phase-locked loop design parameters , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[8]  Jin-Sheng Wang,et al.  A PVT tolerant 0.18MHz to 600MHz self-calibrated digital PLL in 90nm CMOS process , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[9]  Shen-Iuan Liu,et al.  A Phase-Locked Loop With Background Leakage Current Compensation , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

[10]  Chulwoo Kim,et al.  A 10MHz to 315MHz cascaded hybrid PLL with piecewise linear calibrated TDC , 2009, 2009 IEEE Custom Integrated Circuits Conference.

[11]  Chua-Chin Wang,et al.  All-Digital Frequency Synthesizer Using a Flying Adder , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

[12]  Ching-Che Chung,et al.  A portable digitally controlled oscillator using novel varactors , 2005, IEEE Trans. Circuits Syst. II Express Briefs.

[13]  Takamoto Watanabe,et al.  An all-digital PLL for frequency multiplication by 4 to 1022 with seven-cycle lock time , 2003 .

[14]  Enrico Temporiti,et al.  A 3GHz Fractional-N All-Digital PLL with Precise Time-to-Digital Converter Calibration and Mismatch Correction , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[15]  Ping-Ying Wang,et al.  A Fractional Spur-Free ADPLL with Loop-Gain Calibration and Phase-Noise Cancellation for GSM/GPRS/EDGE , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[16]  J.G. Maneatis,et al.  Low-jitter and process independent DLL and PLL based on self biased techniques , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[17]  A. Hajimiri,et al.  Jitter and phase noise in ring oscillators , 1999, IEEE J. Solid State Circuits.

[18]  Liming Xiu.  A Flying-Adder PLL technique enabling novel approaches for video/graphic applications , 2008, IEEE Transactions on Consumer Electronics.

[19]  Sung-Hyun Yang,et al.  A Digital PLL with 5-Phase Digital PFD for Low Long-term Jitter Clock Recovery , 2006, IEEE Custom Integrated Circuits Conference 2006.

[20]  P. Nilsson,et al.  A digitally controlled PLL for SoC applications , 2004, IEEE Journal of Solid-State Circuits.

[21]  K. Muhammad,et al.  All-digital PLL and transmitter for mobile phones , 2005, IEEE Journal of Solid-State Circuits.