Merging path and gshare indexing in perceptron branch prediction

We introduce the hashed perceptron predictor, which merges the concepts behind the gshare, path-based and perceptron branch predictors. This predictor can achieve superior accuracy to a path-based and a global perceptron predictor, previously the most accurate dynamic branch predictors known in the literature. We also show how such a predictor can be ahead pipelined to yield one cycle effective latency. On the SPECint2000 set of benchmarks, the hashed perceptron predictor improves accuracy by up to 15.6% over a MAC-RHSP and 27.2% over a path-based neural predictor.

[1]  Andreas Moshovos.  Checkpointing alternatives for high performance, power-aware processors , 2003, ISLPED '03.

[2]  Brad Calder,et al.  Automatically characterizing large scale program behavior , 2002, ASPLOS X.

[3]  Daniel A. Jiménez,et al.  Neural methods for dynamic branch prediction , 2002, TOCS.

[4]  Yiannakis Sazeides,et al.  Design tradeoffs for the Alpha EV8 conditional branch predictor , 2002, ISCA.

[5]  Sally A. McKee,et al.  On Accurate and Efficient Perceptron-Based Branch Prediction , 2004 .

[6]  Doug Burger,et al.  Evaluating Future Microprocessors: the SimpleScalar Tool Set , 1996 .

[7]  S. McFarling.  Combining Branch Predictors , 1993 .

[8]  Kevin Skadron,et al.  Power-aware branch prediction: characterization and design , 2004, IEEE Transactions on Computers.

[9]  Yale N. Patt,et al.  Variable length path branch prediction , 1998, ASPLOS VIII.

[10]  Gabriel H. Loh,et al.  Simulation Differences Between Academia and Industry: A Branch Prediction Case Study , 2005, IEEE International Symposium on Performance Analysis of Systems and Software, 2005. ISPASS 2005..

[11]  Philippe Roussel,et al.  The microarchitecture of the intel pentium 4 processor on 90nm technology , 2004 .

[12]  Margaret Martonosi,et al.  Improving prediction for procedure returns with return-address-stack repair mechanisms , 1998, Proceedings. 31st Annual ACM/IEEE International Symposium on Microarchitecture.

[13]  Daniel A. Jiménez,et al.  Fast Path-Based Neural Branch Prediction , 2003, MICRO.

[14]  Yale N. Patt,et al.  The agree predictor: a mechanism for reducing negative branch history interference , 1997, ISCA '97.

[15]  André Seznec,et al.  Effective ahead pipelining of instruction block address generation , 2003, ISCA '03.

[17]  Daniel A. Jiménez,et al.  Dynamic branch prediction with perceptrons , 2001, Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture.

[18]  Daniel A. Jiménez.  Idealized Piecewise Linear Branch Prediction , 2005, J. Instr. Level Parallelism.

[19]  Haitham Akkary,et al.  Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors , 2003, MICRO.

[20]  David J. Sager,et al.  The microarchitecture of the Pentium 4 processor , 2001 .

[21]  Daniel A. Jiménez,et al.  The impact of delay on the design of branch predictors , 2000, MICRO 33.

[22]  André Seznec.  The O-GEHL branch predictor , 2004 .

[23]  Pascal Sainrat,et al.  Multiple-block ahead branch predictors , 1996, ASPLOS VII.

[24]  StarkJared,et al.  Variable length path branch prediction , 1998 .

[25]  Dirk Grunwald,et al.  Next cache line and set prediction , 1995, Proceedings 22nd Annual International Symposium on Computer Architecture.

[26]  Lucian N. Vintan,et al.  Towards a high performance neural branch predictor , 1999, IJCNN'99. International Joint Conference on Neural Networks. Proceedings (Cat. No.99CH36339).

[27]  Josep Llosa,et al.  Out-of-order commit processors , 2004, 10th International Symposium on High Performance Computer Architecture (HPCA'04).

[28]  Kevin Skadron,et al.  An ahead pipelined alloyed perceptron with single cycle access time , 2004 .