A high-speed 8-bit D/A converter has been fabricated in a 2-/spl mu/m CMOS technology. In order to achieve high accuracy, a current-cell matrix configuration and a switching sequence called symmetrical switching have been used. The mismatch problem of small-size transistors has been relaxed by this matrix configuration. The linearity error caused by an undesirable current distribution of the current sources has been reduced by symmetrical switching. A high-speed decoding circuit and a fast-setting current source have been developed. The experimental results show that the maximum conversion rate is 80 MHz, a typical DC integral linearity error is 0.38 LSB, a typical DC differential linearity error is 0.22 LSB, and the maximum power consumption is 145 mW. The chip size is 1.85 mm/spl times/2.05 mm.
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