Gallager B Decoder on Noisy Hardware
暂无分享,去创建一个
Lara Dolecek | S. M. Sadegh Tabatabaei Yazdi | Hyungmin Cho | L. Dolecek | Hyungmin Cho | S. M. Sadegh Tabatabaei Yazdi
[1] Jie Han,et al. A system architecture solution for unreliable nanoelectronic devices , 2002 .
[2] Joel Emer,et al. A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..
[3] Nicholas Pippenger,et al. On networks of noisy gates , 1985, 26th Annual Symposium on Foundations of Computer Science (sfcs 1985).
[4] Quinn Jacobson,et al. ERSA: error resilient system architecture for probabilistic applications , 2010, DATE 2010.
[5] Subhasish Mitra,et al. Robust System Design to Overcome CMOS Reliability Challenges , 2011, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.
[6] J. Neumann. Probabilistic Logic and the Synthesis of Reliable Organisms from Unreliable Components , 1956 .
[7] Jehoshua Bruck,et al. Stochastic switching circuit synthesis , 2008, 2008 IEEE International Symposium on Information Theory.
[8] Lav R. Varshney,et al. Performance of LDPC Codes Under Faulty Iterative Decoding , 2008, IEEE Transactions on Information Theory.
[9] Keith M. Chugg,et al. On the Error Tolerance of Iterative Decoder Circuitry ( Invited Paper ) , 2008 .
[10] Sang Joon Kim,et al. A Mathematical Theory of Communication , 2006 .
[11] Shashi Kiran Chilappagari,et al. Analysis of One Step Majority Logic Decoders Constructed From Faulty Gates , 2006, 2006 IEEE International Symposium on Information Theory.
[12] Robert G. Gallager,et al. Low-density parity-check codes , 1962, IRE Trans. Inf. Theory.
[13] Bane V. Vasic,et al. Analytical Performance of One-Step Majority Logic Decoding of Regular LDPC Codes , 2007, 2007 IEEE International Symposium on Information Theory.
[14] Shashi Kiran Chilappagari,et al. Reliable Memories Built from Unreliable Components Based on Expander Graphs , 2007, ArXiv.
[15] Todd M. Austin,et al. DIVA: a reliable substrate for deep submicron microarchitecture design , 1999, MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture.
[16] D. Spielman,et al. Expander codes , 1996 .
[17] Jie Zhang,et al. Robust System Design , 2010, 2010 23rd International Conference on VLSI Design.
[18] Michael G. Taylor. Reliable information storage in memories designed from unreliable components , 1968 .
[19] Lara Dolecek,et al. Probabilistic analysis of Gallager B faulty decoder , 2012, 2012 IEEE International Conference on Communications (ICC).
[20] Norbert Wehn,et al. A Case Study on Error Resilient Architectures for Wireless Communication , 2012, ARCS.
[21] Ravishankar K. Iyer,et al. A Codesigned Fault Tolerance System for Heterogeneous Many-Core Processors , 2011, 2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum.
[22] Rüdiger L. Urbanke,et al. The capacity of low-density parity-check codes under message-passing decoding , 2001, IEEE Trans. Inf. Theory.
[23] Sujit Dey,et al. Evaluating Transient Error Effects in Digital Nanometer Circuits , 2007, IEEE Transactions on Reliability.
[24] Shashi Kiran Chilappagari,et al. An Information Theoretical Framework for Analysis and Design of Nanoscale Fault-Tolerant Memories Based on Low-Density Parity-Check Codes , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.
[25] B. Vasic,et al. Fault Tolerant Memories Based on Expander Graphs , 2007, 2007 IEEE Information Theory Workshop.
[26] Jehoshua Bruck,et al. On the expressibility of stochastic switching circuits , 2009, 2009 IEEE International Symposium on Information Theory.
[27] Christer Svensson,et al. Noise in digital dynamic CMOS circuits , 1994 .
[28] Chen Chang,et al. BEE3: Revitalizing Computer Architecture Research , 2009 .
[29] Péter Gács,et al. Lower bounds for the complexity of reliable Boolean circuits with noisy gates , 1994, IEEE Trans. Inf. Theory.
[30] Sanjukta Bhanja,et al. Probabilistic Error Modeling for Nano-Domain Logic Circuits , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[31] Yong Li. The Design and Simulation of q-ary LDPC Codes Based on the PEG algorithm , 2005 .
[32] Daniel J. Costello,et al. Error Control Coding, Second Edition , 2004 .
[33] Shu Lin,et al. Error Control Coding , 2004 .
[34] Avi Pfeffer,et al. Loopy Belief Propagation as a Basis for Communication in Sensor Networks , 2002, UAI.
[35] André DeHon,et al. Fault Secure Encoder and Decoder for NanoMemory Applications , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[36] Ken Mai,et al. The future of wires , 2001, Proc. IEEE.
[37] Daniel A. Spielman,et al. Highly fault-tolerant parallel computation , 1996, Proceedings of 37th Conference on Foundations of Computer Science.