Enhanced Lithographic Imaging Layer Meets Semiconductor Manufacturing Specification a Decade Early

Lithography followed by plasma etching is the standard method for manufacturing microelectronics. Requirements on lateral resolution and vertical dimensions translate into signifi cant engineering challenges for the lithographic imaging layer (resist). The resist needs to have high resolution, little line-edge roughness, high resistance to plasma etching, and signifi cant mechanical stiffness to prevent pattern collapse during wet development. Presently, no resist material satisfi es all these requirements simultaneously. We show that many of the qualities of an ideal resist layer can be achieved by improving plasma etch resistance of poly(methyl methacrylate) (PMMA). PMMA treated with aluminum oxide sequential infi ltration synthesis (SIS) allows dense high-resolution (sub-20 nm) patterns to be defi ned and transferred deeply into silicon without an intermediate hard mask. The improved etch resistance of the SISPMMA also allows the aspect-ratio of the resist structures to be decreased below the limit of wet collapse, thereby meeting the requirements of the International Technology Roadmap for Semiconductors up to year 2022. Lithography and plasma etching form the cornerstones of nanoscale manufacturing. Initially developed for the microelectronics industry, these techniques are also essential to other technologies, such as micro-electro-mechanical and microfl uidic systems. Indeed, the physical realization of any system with nanoscale components requires a certain degree of topdown patterning. In lithography, an imaging layer (resist) sensitive to light or electrons is exposed to the image of a fi ne pattern and developed in wet chemicals. Plasma etching is then used to transfer the pattern in the imaging layer to a material of interest. These procedures are then repeated many times to complete a functional system. Central to the success of these top-down manufacturing methods is the ability of the imaging layer to capture fi ne features with high fi delity. In addition, the imaging layer needs to play the role of etch mask. It needs to be resistant to plasma etching to allow pattern transfer into the underlying material. The imaging layer, however, is usually carbon-based and has little resistance to plasma etching. This non-ideality is

[1]  S. Darling,et al.  Etch Properties of Resists Modified by Sequential Infiltration Synthesis , 2011 .

[2]  Leonidas E. Ocola,et al.  Enhanced polymeric lithography resists via sequential infiltration synthesis , 2011 .

[3]  G. Grenci,et al.  Boehmite filled hybrid sol-gel system as directly writable hard etching mask for pattern transfer , 2011 .

[4]  Gerard Ghibaudo,et al.  Mobility analysis of surface roughness scattering in FinFET devices , 2011 .

[5]  Leonidas E. Ocola,et al.  Enhanced Block Copolymer Lithography Using Sequential Infiltration Synthesis , 2011 .

[6]  Min Chen,et al.  Statistical Modeling and Simulation of Threshold Variation Under Random Dopant Fluctuations and Line-Edge Roughness , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[7]  Seth B Darling,et al.  A route to nanoscopic materials via sequential infiltration synthesis on block copolymer templates. , 2011, ACS nano.

[8]  D. Graves,et al.  Plasma-polymer interactions: A review of progress in understanding polymer resist mask durability during plasma etching for nanoscale fabrication , 2011 .

[9]  S. Darling,et al.  Nanoscopic Patterned Materials with Tunable Dimensions via Atomic Layer Deposition on Block Copolymers , 2010, Advanced materials.

[10]  Nicolò Speciale,et al.  VDD scalability of FinFET SRAMs: Robustness of different design options against LER-induced variations , 2010 .

[11]  E. Gogolides,et al.  Optimized surface silylation of chemically amplified epoxidized photoresists for micromachining applications , 2010 .

[12]  M. Z. R. Khan,et al.  Spin-coatable HfO2 resist for optical and electron beam lithographies , 2010 .

[13]  L. Pain,et al.  Study on line edge roughness for electron beam acceleration voltages from 50to5kV , 2009 .

[14]  Bruce Harteneck,et al.  25 nm mechanically buttressed high aspect ratio zone plates: Fabrication and performance , 2004 .

[15]  Gregg M. Gallatin,et al.  Effect of thin-film imaging on line edge roughness transfer to underlayers during etch processes , 2004 .

[16]  Franco Cerrina,et al.  Line edge roughness of sub-100 nm dense and isolated features: Experimental study , 2003 .

[17]  D. Schmitt-Landsiedel,et al.  High Precision Etching of Si / SiO2 on a High-Density Helicon Etcher for Nanoscale Devices , 2003 .

[18]  Shiying Xiong,et al.  Gate line-edge roughness effects in 50-nm bulk MOSFET devices , 2002, SPIE Advanced Lithography.

[19]  C.H. Diaz,et al.  An experimentally validated analytical model for gate line-edge roughness (LER) effects on technology scaling , 2001, IEEE Electron Device Letters.

[20]  H. Ootera,et al.  Profile evolution during polysilicon gate etching with low-pressure high-density Cl2/HBr/O2 plasma chemistries , 2001 .

[21]  Brian Osborn,et al.  Study of the fundamental contributions to line edge roughness in a 193 nm, top surface imaging system , 2000 .

[22]  H. Morimoto,et al.  High sensitive negative silylation process for 193nm lithography , 2000 .

[23]  Takahiro Matsuo,et al.  Reduction of line edge roughness in the top surface imaging process , 1998 .

[24]  F. V. Roey,et al.  Integrated Silylation and Dry Development of Resist for Sub 0.15μm Top Surface Imaging Applications , 1998 .

[25]  Omkaram Nalamasu,et al.  Application of Plasmask R resist and the DESIRE process to lithography at 248 nm , 1990 .

[26]  T. Mourier,et al.  PRIME process for deep UV and e-beam lithography , 1990 .

[27]  James W. Thackeray,et al.  Approaches to deep ultraviolet photolithography utilizing acid hardened resin photoresist systems , 1989 .