Robust configurable system design with built-in self-healing

The new generations of SRAM-based FPGA (Field Programmable Gate Array) devices, built on nanometre technology, are the preferred choice for the implementation of reconfigurable computing platforms. However, their vulnerability to hard and soft errors is a major weakness to robust system design based on FPGAs. In this paper, a novel Built-In Self-Healing (BISH) methodology, based on modular redundancy and on selfreconfiguration, is proposed. A soft microprocessor core implemented in the FPGA is responsible for the management and execution of all the BISH procedures. Fault detection and diagnosis is followed by repairing actions, taking advantage of the self-configuration features. Meanwhile, modular redundancy assures that the system still works correctly. This approach leads to a robust system design able to assure high reliability, availability and data integrity.

[1]  Lorena Anghel,et al.  Concurrent Checking for VLSI , 1999 .

[2]  Carl Carmichael,et al.  Triple Module Redundancy Design Techniques for Virtex FPGAs, Application Note 197 , 2001 .

[3]  J. von Neumann,et al.  Probabilistic Logic and the Synthesis of Reliable Organisms from Unreliable Components , 1956 .

[4]  M. Caffrey,et al.  Correcting single-event upsets through virtex partial configuration , 2000 .

[5]  P. K. Lala Self-Checking and Fault-Tolerant Digital Design , 1995 .

[6]  Edward J. McCluskey,et al.  Dependable Computing and Online Testing in Adaptive and Configurable Systems , 2000, IEEE Des. Test Comput..

[7]  M. Abramovici,et al.  Improving on-line BIST-based diagnosis for roving STARs , 2000, Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646).

[8]  Charles E. Stroud,et al.  Using roving STARs for on-line testing and diagnosis of FPGAs in fault-tolerant applications , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[9]  Gustavo Ribeiro Alves,et al.  Active replication: towards a truly SRAM-based FPGA on-line concurrent testing , 2002, Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW 2002).

[10]  Gustavo Ribeiro Alves,et al.  Run-time management of logic resources on reconfigurable systems , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[11]  J. H. Lala,et al.  Architectural principles for safety-critical real-time applications , 1994, Proc. IEEE.

[12]  M. Caffrey,et al.  SEU Mitigation Techniques for Virtex FPGAs in Space Applications , 1999 .

[13]  BaumannRobert Soft Errors in Advanced Computer Systems , 2005 .

[14]  N. Seifert,et al.  Robust system design with built-in soft-error resilience , 2005, Computer.

[15]  Scott McMillan,et al.  A lightweight approach for embedded reconfiguration of FPGAs , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[16]  R. Reed,et al.  Heavy ion and proton-induced single event multiple upset , 1997 .

[17]  Edward J. McCluskey,et al.  Word-voter: a new voter design for triple modular redundant systems , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[18]  Delon Levi,et al.  JBits: Java based interface for reconfigurable computing , 1999 .