A fractional sample rate conversion filter for a software radio receiver on FPGA

Sample rate conversion for a software radio receiver is one of the critical tasks. Due to the phenomenon of bandpass sampling, digitization of a very high intermediate frequency incorporating different wireless communication standards has to undergo sample rate conversion ranging from a factor of 4 to 400. In this paper, an architectural implementation of Digital Down Converter (DDC) for multi-standard radio based on multiplexed Cascaded Integrator Comb (CIC) decimation filters is presented. To compensate the gain droop in the pass band of the CIC filter, a droop compensation filter is needed. In addition to this an interpolation filter is required to match the symbol rate of the standard. Hence, a joint compensation and interpolation filter is designed based on the transposed Farrow structure. The designed filter offers flexibility due to the computation of coefficients using frequency domain polynomials rather than time domain information. A VHDL model for the filter has been developed and the same has been functionally simulated using the Xilinx FPGA device XC6VCX240t-2FF484. The results show that a reconfigurable Farrow filter can be easily designed for matching the symbol rate of any radio standard with the same hardware resources.

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