Signal suppression model and an on-chip countermeasure to power analysis attacks

There are several attacks that exploit the presence of side channels in hardware implementations of cryptographic algorithms to extract secret data. Differential Power Analysis (DPA) and Simple Power Analysis (SPA) attacks sense the power consumption of the hardware to extract the secret cryptographic key. These attacks either directly examine the power traces or carry out statistical operations on the power traces obtained from the hardware while executing the cryptographic algorithm. This dissertation presents a signal suppression circuit (SSC) that can be added to crypto-hardware to suppress information leakage through the power supply pin side channel. Simulation data on actual power traces of a 8-bit microcontroller running the Data Encryption Standard (DES) show that the SSC attenuates the information signal by a factor of 0.046. A signal and noise model has been developed which shows that the SSC increases the attacker's workload, to successfully carry out a DPA attack, by the inverse of the square of the attenuation. A power save version of the SSC has been designed. This circuit offers a power-security tradeoff to the designer. The countermeasure places no constraints on the design of the hardware under protection.