Power and Stability Analysis of a Proposed 12T MTCMOS SRAM Cell for Low Power Devices

This paper focuses on the power dissipations at different temperatures and stability analysis at different pull-up ratios of a novel low power 12T MTCMOS SRAM cell. Because of MTCMOS technology, the SRAM cell is having low VT (LVT) transistors and there are two high VT (HVT) Sleep transistors as well. Sleep transistors and a LVT Transmission gate (TG) in conjunction are used for reducing the wake up power during transition from sleep mode to active mode and sleep power during transition from sleep mode to active mode for writing operations of the SRAM cell. This reduces the static energy dissipation of the cell. In the proposed structure two additional voltage sources are also used, one connected with the bit line and the other one connected with the bitbar line in order to reduce the swing voltage at the output nodes of the bit and the bitbar lines. The reduction in swing causes the reduction in dynamic power dissipation. Because of very low leakage currents in MTCMOS technology, the stability of data retention is also enhanced. Simulation results of power dissipation and stability of the proposed SRAM cell have been determined and compared to those of some other exiting models of SRAM cell. The proposed cell dissipates less power at different temperatures and better stability at different pull-up ratios than the other SRAM models. Simulation has been done in 45nm CMOS environment. Microwind 3.1 is used for schematic design and layout design purpose.

[1]  Mohab Anis,et al.  Statistical Design of the 6T SRAM Bit Cell , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[2]  Ajay Kumar Singh,et al.  A proposed symmetric and balanced 11-T SRAM cell for lower power consumption , 2009, TENCON 2009 - 2009 IEEE Region 10 Conference.

[3]  S. Areibi,et al.  Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique , 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).

[4]  Magdy A. Bayoumi,et al.  Low-Power Cache Design Using 7T SRAM Cell , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

[5]  Anantha Chandrakasan,et al.  MTCMOS hierarchical sizing based on mutual exclusive discharge patterns , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[6]  Feipei Lai,et al.  Zero-aware asymmetric SRAM cell for reducing cache power in writing zero , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[7]  Bharadwaj Amrutur,et al.  Techniques to reduce power in fast wide memories [CMOS SRAMs] , 1994, Proceedings of 1994 IEEE Symposium on Low Power Electronics.

[8]  Zhiyu Liu,et al.  Characterization of a Novel Nine-Transistor SRAM Cell , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[9]  W. Dehaene,et al.  Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies , 2006, IEEE Journal of Solid-State Circuits.

[10]  Kaushik Roy,et al.  A Low-Power SRAM Using Bit-Line Charge-Recycling , 2008, IEEE Journal of Solid-State Circuits.

[11]  Akira Tada,et al.  Low Power SRAM with Boost Driver Generating Pulsed Word Line Voltage for Sub-1V Operation , 2008, J. Comput..

[12]  Satoshi Shigematsu,et al.  A shared-bitline SRAM cell architecture for 1-V ultra low-power word-bit configurable macrocells , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

[13]  David Blaauw,et al.  Yield-Driven Near-Threshold SRAM Design , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[14]  Kaushik Roy,et al.  A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS , 2009, IEEE Journal of Solid-State Circuits.

[15]  T. Sakurai,et al.  90% write power-saving SRAM using sense-amplifying memory cell , 2004, IEEE Journal of Solid-State Circuits.