Characteristics of Recessed-Gate TFETs With Line Tunneling

In this paper, we propose a recessed-gate tunneling field-effect transistor (TFET) to improve the on current of TFETs by increasing the tunnel area with line tunneling. We investigate the effects of the recessed-body thickness and the doping level on the device performance. For optimal device structures, our proposed n-TFET reaches <inline-formula> <tex-math notation="LaTeX">$1.44 \times 10^{-6}$ </tex-math></inline-formula> A/<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> of on current and <inline-formula> <tex-math notation="LaTeX">$3.22 \times 10^{9}$ </tex-math></inline-formula> ON/ OFF current ratio. A minimum subthreshold swing SS<inline-formula> <tex-math notation="LaTeX">$_{{\textsf {min}}} = 28.3$ </tex-math></inline-formula> mV/dec and an average swing SS<inline-formula> <tex-math notation="LaTeX">$_{{\textsf {avg}}} = 59.8$ </tex-math></inline-formula> mV/dec over seven orders of drain current are achieved. In addition, complementary TFET inverters show good noise margins of <inline-formula> <tex-math notation="LaTeX">$\textsf {NM}_{H} = 65$ </tex-math></inline-formula> mV (38.5 % <inline-formula> <tex-math notation="LaTeX">$V_{{\textsf {DD}}}$ </tex-math></inline-formula>) and NM<inline-formula> <tex-math notation="LaTeX">$_{L} = 77$ </tex-math></inline-formula> mV (32.5 % <inline-formula> <tex-math notation="LaTeX">$V_{{\textsf {DD}}}$ </tex-math></inline-formula>) and also a high voltage gain even at <inline-formula> <tex-math notation="LaTeX">$V_{{\textsf {DD}}} = 0.2$ </tex-math></inline-formula> V.

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