Versatile macromodel for the power supply of submicronic CMOS microprocessors based on voltage down DC-DC converter

A new SPICE macromodel that simulates a microprocessor loading impedance at the power supply is presented. This macro model has been especially created to accelerate the time to market in the design of DC-DC voltage converters used to supply submicronic digital integrated circuits. The proposed macromodel has been successfully compared to measurements for a dedicated test-chip implemented in CMOS 0.35 /spl mu/m from STM. The test-chip includes a 16 bit microprocessor supplied by a voltage down converter. SPICE simulations and measurements demonstrate the efficiency of the proposed model.

[1]  Alexander Chatzigeorgiou,et al.  A modeling technique for CMOS gates , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Jeong-Taek Kong,et al.  Methods to improve digital MOS macromodel accuracy , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Nicholas C. Rumin,et al.  Inverter models of CMOS gates for supply current and delay evaluation , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Daniel Auvergne,et al.  A novel macromodel for power estimation in CMOS structures , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  D. Auvergne,et al.  A comprehensive delay macro modeling for submicrometer CMOS logics , 1999, IEEE J. Solid State Circuits.

[6]  Spiridon Nikolaidis,et al.  Analytical transient response and propagation delay evaluation of the CMOS inverter for short-channel devices , 1998, IEEE J. Solid State Circuits.

[7]  Jeong-Taek Kong,et al.  Performance estimation of complex MOS gates , 1997 .