Electrical-Based ESD Characterization of Ultrathin-Body SOI MOSFETs

The electrostatic-discharge sensitivity of fully depleted SOI MOSFETs with ultrathin silicon body and ultrathin gate oxide is studied. An original and detailed electrical analysis is carried out in order to investigate the degradation of the electrical DC parameters and classify the observed failure modes and mechanisms. The impact of device geometry and strain engineering is also analyzed.

[1]  Philippe Roussel,et al.  Gate oxide breakdown in FET devices and circuits: From nanoscale physics to system-level reliability , 2007, Microelectron. Reliab..

[2]  Christian Russ ESD issues in advanced CMOS bulk and FinFET technologies: Processing, protection devices and circuit strategies , 2008, Microelectron. Reliab..

[3]  Impact of strain engineering and channel orientation on the ESD performance of nanometer scale CMOS devices , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[4]  R. Rooyackers,et al.  Electrical and thermal scaling trends for SOI FinFET ESD design , 2009, 2009 31st EOS/ESD Symposium.

[5]  Guido Groeseneken,et al.  Influence of gate length on ESD-performance for deep sub micron CMOS technology , 1999, Electrical Overstress/Electrostatic Discharge Symposium Proceedings. 1999 (IEEE Cat. No.99TH8396).

[6]  Guido Groeseneken,et al.  New insights in the relation between electron trap generation and the statistical properties of oxide breakdown , 1998 .

[7]  Akram A. Salman,et al.  ESD-induced oxide breakdown on self-protecting GG-nMOSFET in 0.1-/spl mu/m CMOS technology , 2003 .

[8]  E. Simoen,et al.  Performance and Reliability of Strained-Silicon nMOSFETs With SiN Cap Layer , 2007, IEEE Transactions on Electron Devices.

[9]  Guido Groeseneken,et al.  Hot carrier degradation and ESD in submicrometer CMOS technologies: how do they interact? , 2001 .

[10]  S. Sugahara,et al.  Carrier-Transport-Enhanced Channel CMOS for Improved Power Consumption and Performance , 2008, IEEE Transactions on Electron Devices.

[11]  Eddy Simoen,et al.  Impact strain engineering on gate stack quality and reliability , 2008 .

[12]  Akram A. Salman,et al.  NMOSFET ESD self-protection strategy and underlying failure mechanism in advanced 0.13-/spl mu/m CMOS technology , 2002 .

[13]  H. Gossner,et al.  Reliability aspects of gate oxide under ESD pulse stress , 2007 .

[14]  Chenming Hu,et al.  Ultrathin-body SOI MOSFET for deep-sub-tenth micron era , 2000, IEEE Electron Device Letters.

[15]  M. Kerber,et al.  Soft breakdown and hard breakdown in ultra-thin oxides , 2001, Microelectron. Reliab..

[16]  Seung Hwan Lee,et al.  Large scale integration and reliability consideration of triple gate transistors , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[17]  Sung-Mo Kang,et al.  EOS/ESD protection circuit design for deep submicron SOI technology , 1995, Electrical Overstress/Electrostatic Discharge Symposium Proceedings.

[18]  Sorin Cristoloveanu,et al.  Frontiers of silicon-on-insulator , 2003 .

[19]  R. Rooyackers,et al.  Impact of Strain on ESD Robustness of FinFET Devices , 2008, 2008 IEEE International Electron Devices Meeting.

[20]  E. Simoen,et al.  Electrostatic discharge effects in Fully Depleted SOI MOSFETs with ultra-thin gate oxide and different strain-inducing techniques , 2008, EOS/ESD 2008 - 2008 30th Electrical Overstress/Electrostatic Discharge Symposium.

[21]  Souvick Mitra,et al.  ESD time-domain characterization of high-k gate dielectric in a 32 nm CMOS technology , 2009, 2009 31st EOS/ESD Symposium.

[22]  S. Dey,et al.  Considerations for evaluating hot-electron reliability of strained Si n-channel MOSFETs , 2005, Microelectron. Reliab..

[23]  A. Bravaix,et al.  Ultra-thin gate oxide reliability in the ESD time domain , 2006, 2006 Electrical Overstress/Electrostatic Discharge Symposium.

[24]  Kaustav Banerjee,et al.  Analysis of nonuniform ESD current distribution in deep submicron NMOS transistors , 2002 .

[25]  Amitava Chatterjee,et al.  Hot-electron reliability and ESD latent damage , 1988 .

[26]  S. Prasad,et al.  Channel width dependence of NMOSFET hot carrier degradation , 2003 .

[27]  R. Rooyackers,et al.  Characterization and Optimization of Sub-32-nm FinFET Devices for ESD Applications , 2008, IEEE Transactions on Electron Devices.

[28]  Vladislav A. Vashchenko,et al.  Physical Limitations of Semiconductor Devices , 2008 .