Variable Precision Floating Point Reciprocal, Division and Square Root for Major FPGA Vendors

Variable precision floating point operations have various fields of applications including scientific computing and signal processing. Field Programmable Gate Arrays (FPGAs) are a good platform to accelerate such applications because of their flexibility, low development time and cost compared to Application Specific Integrated Circuits (ASICs) and low power consumption compared to Graphics Processing Units (GPUs). Increasingly scientists are interested in variable precision floating point operations not limited to single or double precision operations implemented on FPGAs, in order to make those operations more resource efficient and more suited to their own applications. Among those operations, the performance of reciprocal, division and square root can differ based on the algorithm implemented. They can highly affect the total performance of the application running them. In this thesis, we improve these three operations using a table based approach. Our implementation is written in Very High Speed Integrated Circuits Hardware Description Language (VHDL) and implemented on FPGAs. These components have been implemented using both Altera and Xilinx development environments, the two major FPGA vendors. Also these implementations provide a good tradeoff among hardware resource utilization, maximum clock frequency and latency. Users can change the latency by adjusting the parameters of the components. In addition to supporting the IEEE 754 standard representations which include single and double precision, these components can be customized by