Improved Design of 1 T Charge-Modulation Pixel Structure for Small-Size and Low-Dark-Current Achievements

A ring-gate design of 1T (single-transistor) chargemodulation pixel structure is proposed. It obviates the need to employ STI (shallow trench isolation) for avoiding crosstalk. This enables achievements of smaller pixel size and/or higher fill factor. It also reduces dark current by limiting peripheral leakage current contribution and minimizing band-to-band tunneling effect. A test chip integrating an array of 1.4μm-pitch, 50%-fill-factor pixels is designed in a 0.13μm CMOS technology. The measured pixel characteristics are compared with those from a 2.2μmpitch, 46%-fill-factor previous design (also in a 0.13μm CMOS process). The comparison shows that the 1.4μmpitch ring-gate pixel has an improved conversion gain (CG) and a degraded full well capacity (FWC). It also shows substantial reductions on dark current, temporal noise and FPN. The resulting signal-to-noise ratio outweighs degradation of FWC, which also improves dynamic range.