DCM demapper for MB-OFDM on FPGA

This paper presents the implementation of a dual carrier modulation (DCM) demapper, proposed as part of a MB-OFDM UWB receiver to be integrated in an FPGA. The implemented DCM demapper, together with the FFT and the Viterbi decoder, were implemented in a Xilinx Virtex-5 FPGA. The complete system was modelled and tested with Matlab/Simulink and the part implemented in FPGA was connected to Matlab using the System Generator from Xilinx.