3D-HIM: A 3D High-density Interleaved Memory for bipolar RRAM design
暂无分享,去创建一个
Wei Zhang | Robinson E. Pino | Hai Li | Yi-Chung Chen | Wei Zhang | Hai Helen Li | Yi-Chung Chen | R. Pino
[1] Kaustav Banerjee,et al. Performance analysis and technology of 3-D ICs , 2000, SLIP '00.
[2] Dmitri B Strukov,et al. Four-dimensional address topology for circuits with stacked multilayer crossbar arrays , 2009, Proceedings of the National Academy of Sciences.
[3] R. Rosezin,et al. High density 3D memory architecture based on the resistive switching effect , 2009 .
[4] R. Waser,et al. A multilayer RRAM nanoarchitecture with resistively switching Ag-doped spin-on glass , 2009, 2009 10th International Conference on Ultimate Integration of Silicon.
[5] R. Waser,et al. Integration of GexSe1-x in crossbar arrays for non-volatile memory applications , 2009 .
[6] I. Baek,et al. Multi-layer cross-point binary oxide resistive memory (OxRRAM) for post-NAND storage application , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..
[7] A. C. Madayag,et al. Optimization of spin-on-glass process for multilevel metal interconnects , 2001, Proceedings of the Fourteenth Biennial University/Government/Industry Microelectronics Symposium (Cat. No.01CH37197).
[8] Rainer Waser,et al. Complementary resistive switches for passive nanocrossbar memories. , 2010, Nature materials.
[9] P. Kapur,et al. 3-D ICs: Motivation, performance analysis, and technology , 2000, Proceedings of the 26th European Solid-State Circuits Conference.
[10] Y. Inoue,et al. High Speed Unipolar Switching Resistance RAM (RRAM) Technology , 2006, 2006 International Electron Devices Meeting.
[11] 裕幸 飯田,et al. International Technology Roadmap for Semiconductors 2003の要求清浄度について - シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について - , 2004 .
[12] M. Van Hove,et al. Integration of unlanded via in a non-etchback SOG direct-on-metal approach in 0.25 micron CMOS process , 1998, Proceedings of the IEEE 1998 International Interconnect Technology Conference (Cat. No.98EX102).
[13] Yiran Chen,et al. 3D-ICML: A 3D bipolar ReRAM design with interleaved complementary memory layers , 2011, 2011 Design, Automation & Test in Europe.
[14] Yi-Chang Lu. 3D technology based circuit and architecture design , 2009, 2009 International Conference on Communications, Circuits and Systems.
[15] Jiale Liang,et al. Cross-Point Memory Array Without Cell Selectors—Device Characteristics and Data Storage Pattern Dependencies , 2010, IEEE Transactions on Electron Devices.
[16] Yiran Chen,et al. An overview of non-volatile memory technology and the implication for tools and architectures , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.
[17] Hsien-Hsin S. Lee,et al. Architectural evaluation of 3D stacked RRAM caches , 2009, 2009 IEEE International Conference on 3D System Integration.
[18] W. Lu,et al. High-density Crossbar Arrays Based on a Si Memristive System , 2008 .
[19] Thomas H. Lee,et al. 512-Mb PROM with a three-dimensional array of diode/antifuse memory cells , 2003 .
[20] M.H. Kryder,et al. After Hard Drives—What Comes Next? , 2009, IEEE Transactions on Magnetics.
[21] Rainer Waser,et al. Reliability analysis of the low resistance state stability of Ge0.3Se0.7 based solid electrolyte nonvolatile memory cells , 2009 .