Security Threats and Countermeasures in Three-Dimensional Integrated Circuits

Existing works on Three-dimensional (3D) hardware security focus on leveraging the unique 3D characteristics to address the supply chain attacks that exist in 2D design. However, 3D ICs introduce specific and unexplored challenges as well as new opportunities for managing hardware security. In this paper, we analyze new security threats unique to 3D ICs. The corresponding attack models are summarized for future research. Furthermore, existing representative countermeasures, including split manufacturing, camouflaging, transistor locking, techniques against thermal signal based side-channel attacks, and network-on-chip based shielding plane (NoCSIP) for different hardware threats are reviewed and categorized. Moreover, preliminary countermeasures are proposed to thwart TSV-based hardware Trojan insertion attacks.

[1]  Yuan Xie,et al.  Die-stacking Architecture , 2015, Die-stacking Architecture.

[2]  Yuan Xie,et al.  Cost and Thermal Analysis of High-Performance 2.5D and 3D Integrated Circuit Design Space , 2016, 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

[3]  Ankur Srivastava,et al.  3D/2.5D IC-Based Obfuscation , 2017 .

[4]  Yuan Xie,et al.  Thermal-aware 3D design for side-channel information leakage , 2016, 2016 IEEE 34th International Conference on Computer Design (ICCD).

[5]  Ryan Kastner,et al.  A 3-D Split Manufacturing Approach to Trustworthy System Development , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  R. S. Jagtap,et al.  A Methodology for Early Exploration of TSV Interconnects in 3D Stacked ICs , 2011 .

[7]  Chang-Chi Lee,et al.  An Overview of the Development of a GPU with Integrated HBM on Silicon Interposer , 2016, 2016 IEEE 66th Electronic Components and Technology Conference (ECTC).

[8]  Emre Salman,et al.  Transistor-level camouflaged logic locking method for monolithic 3D IC security , 2016, 2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST).

[9]  Yuan Xie,et al.  Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[10]  Peter Gadfort,et al.  Split-fabrication obfuscation: Metrics and techniques , 2014, 2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST).

[11]  Siddharth Garg,et al.  Securing Computer Hardware Using 3D Integrated Circuit (IC) Technology and Split Manufacturing for Obfuscation , 2013, USENIX Security Symposium.

[12]  Radhika Sanjeev Jagtap,et al.  A Methodology for Early Exploration of TSV Placement Topologies in 3D Stacked ICs , 2012, 2012 15th Euromicro Conference on Digital System Design.

[13]  Michael Bilzor 3D Execution Monitor (3D-EM): Using 3D Circuits to Detect Hardware Malicious Inclusions in General Purpose Processors , 2011 .

[14]  Emre Salman,et al.  Hardware security threats and potential countermeasures in emerging 3D ICs , 2016, 2016 International Great Lakes Symposium on VLSI (GLSVLSI).

[15]  Ryan Kastner,et al.  Hardware trust implications of 3-D integration , 2010, WESS '10.

[16]  Mark Mohammad Tehranipoor,et al.  Security and Vulnerability Implications of 3D ICs , 2016, IEEE Transactions on Multi-Scale Computing Systems.

[17]  Liu Liu,et al.  Leveraging 3D technologies for hardware security: Opportunities and challenges , 2016, 2016 International Great Lakes Symposium on VLSI (GLSVLSI).

[18]  Narayanan Vijaykrishnan,et al.  Interconnect and thermal-aware floorplanning for 3D microprocessors , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

[19]  Christian Bernard,et al.  3D advanced integration technology for heterogeneous systems , 2015, 2015 International 3D Systems Integration Conference (3DIC).

[20]  M. Koyanagi,et al.  Novel reconfigured wafer-to-wafer (W2W) hybrid bonding technology using ultra-high density nano-Cu filaments for exascale 2.5D/3D integration , 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

[21]  Ramesh Karri,et al.  A Primer on Hardware Security: Models, Methods, and Metrics , 2014, Proceedings of the IEEE.

[22]  Qiaosha Zou,et al.  Overview of 3-D Architecture Design Opportunities and Techniques , 2017, IEEE Design & Test.

[23]  Jeyavijayan Rajendran,et al.  Is split manufacturing secure? , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[24]  Erik Jan Marinissen Challenges and emerging solutions in testing TSV-based 2 1 over 2D- and 3D-stacked ICs , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[25]  Yuan Xie,et al.  Cost analysis and cost-driven IP reuse methodology for SoC design based on 2.5D/3D integration , 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[26]  S. K. Kim,et al.  Three-dimensional integration: technology, use, and issues for mixed-signal applications , 2003 .

[27]  Sung Kyu Lim,et al.  A 14nm FinFET transistor-level 3D partitioning design to enable high-performance and low-cost monolithic 3D IC , 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

[28]  Jason Cong,et al.  Three-Dimensional Integrated Circuit Design: EDA, Design and Microarchitectures , 2009 .

[29]  Ankur Srivastava,et al.  Security-Aware Design Flow for 2.5D IC Technology , 2015, TrustED@CCS.

[30]  Ian O'Connor,et al.  Heterogeneous system design platform and perspectives for 3D integration , 2009, 2009 International Conference on Microelectronics - ICM.

[31]  Mark Mohammad Tehranipoor,et al.  Efficient and secure split manufacturing via obfuscated built-in self-authentication , 2015, 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

[32]  Swarup Bhunia,et al.  Hardware Protection through Obfuscation , 2017 .