Two new techniques for compiled multi-delay simulation
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[1] Craig Hansen,et al. Hardware logic simulation by compilation , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..
[2] Zhicheng Wang,et al. LECSIM: a levelized event driven compiled logic simulation , 1991, DAC '90.
[3] Barry K. Rosen,et al. HSS--A High-Speed Simulator , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[4] David M. Lewis. Hierarchical compiled event-driven logic simulation , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[5] Stephen A. Szygenda,et al. A model and implementation of a universal time delay simulator for large digital nets , 1970, AFIPS '70 (Spring).
[6] James R. Bell,et al. Threaded code , 1973, CACM.
[7] John J. Zasio,et al. SSIM: A Software Levelized Compiled-Code Simulator , 1987, 24th ACM/IEEE Design Automation Conference.
[8] Peter M. Maurer. The Florida Hardware Design Language , 1990, IEEE Proceedings on Southeastcon.
[9] Zhicheng Wang,et al. Techniques for unit-delay compiled simulation , 1991, DAC '90.
[10] M Chiang,et al. LCC simulators speed development of synchronous hardware , 1986 .
[11] Randal E. Bryant,et al. COSMOS: a compiled simulator for MOS circuits , 1987, DAC '87.