State Machine Design Techniques for Verilog and VHDL

A finite state machine has the general structure shown in Figure 1. The current state of the machine is stored in the state memory, a set of n flip-flops clocked by a single clock signal (hence “synchronous” state machine). The state vector (also current state, or just state) is the value currently stored by the state memory. The next state of the machine is a function of the state vector and the inputs. Mealy outputs are a function of the state vector and the inputs, while Moore outputs are a function of the state vector only.