Bridging the gap between TCAD and ECAD methodologies in deep sub-micron interconnect extraction and analysis

Dominance of interconnect parasitics in impacting functionality, performance and reliability in deep sub-micron (DSM) designs is a well known topic. Reduced metal pitches, process variations, new materials for metallization/dielectrics emphasizes an increased need for "accurate" technology modeling of interconnect. In the mean time, continued design integration, increased chip sizes and market pressures call for faster but "accurate" EDA methodologies and tools. This tutorial provides a complete perspective of the TCAD interconnect modeling issues and how these could be addressed in ECAD methodologies and tools.

[1]  Weikai Sun,et al.  Fast parameters extraction of general three-dimension interconnects using geometry independent measured equation of invariance , 1996, 33rd Design Automation Conference Proceedings, 1996.

[2]  Roland W. Freund,et al.  Reduced-Order Modeling of Large Linear Subcircuits via a Block Lanczos Algorithm , 1995, 32nd Design Automation Conference.

[3]  Roland W. Freund,et al.  Efficient linear circuit analysis by Pade´ approximation via the Lanczos process , 1994, EURO-DAC '94.

[4]  S.G. Duvall,et al.  A practical methodology for the statistical design of complex logic products for performance , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[5]  K. L. Shepard,et al.  Noise in deep submicron digital design , 1996, ICCAD 1996.

[6]  Alberto Sangiovanni-Vincentelli,et al.  Digital sensitivity: predicting signal interaction using functional analysis , 1996, ICCAD 1996.

[7]  Frank Cano,et al.  A practical approach to static signal electromigration analysis , 1998, DAC.

[8]  A. Yang,et al.  Stable and efficient reduction of large, multiport RC networks by pole analysis via congruence transformations , 1996, 33rd Design Automation Conference Proceedings, 1996.

[9]  S. Grout,et al.  Chip hierarchical design system (CHDS): a foundation for timing-driven physical design into the 21st century , 1997, ISPD '97.

[10]  Haifang Liao,et al.  Partitioning and reduction of RC interconnect networks based on scattering parameter macromodels , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[11]  Lawrence T. Pileggi,et al.  Asymptotic waveform evaluation for timing analysis , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[12]  P. Yang,et al.  Multilevel metal capacitance models for CAD design synthesis systems , 1992, IEEE Electron Device Letters.

[13]  M. Bohr.  Interconnect scaling-the real limiter to high performance ULSI , 1995, Proceedings of International Electron Devices Meeting.

[14]  Lawrence T. Pileggi,et al.  PRIMA: passive reduced-order interconnect macromodeling algorithm , 1997, ICCAD 1997.