New Systolic Arrays for C + AB2, Inversion, and Division in GF(2m)

In this paper, we present a new parallel-in parallel-out systolic array with unidirectional data flow for performing the power-sum operation C+AB/sup 2/ in finite fields GF(2/sup m/). The architecture employs the standard basis representation and can provide the maximum throughput in the sense of producing new results at a rate of one per clock cycle. It is highly regular, modular, and, thus, well-suited to VLSI implementation. As compared to a previous systolic power-sum circuit with bidirectional data flow and the same throughput performance, the proposed one has smaller latency, consumes less chip area, and can more easily incorporate fault-tolerant design. Based on the new power-sum circuit, we also propose a parallel-in parallel-out systolic array with the maximum throughput for computing inverses/divisions in GF(2/sup m/). The proposed systolic divider gains advantages over an existing system with the same throughput performance in terms of chip area, latency, and fault tolerance.

[1]  Chin-Liang Wang,et al.  A Systolic Architecture for Computing Inverses and Divisions in Finite Fields GF(2^m) , 1993, IEEE Trans. Computers.

[2]  Shyue-Win Wei.  A Systolic Power-Sum Circuit for GF(2^m) , 1994, IEEE Trans. Computers.

[3]  Trieu-Kien Truong,et al.  A Comparison of VLSI Architecture of Finite Field Multipliers Using Dual, Normal, or Standard Bases , 1988, IEEE Trans. Computers.

[4]  A. Sengupta,et al.  Algorithms for multiplication in Galois field for implementation using systolic arrays , 1988 .

[5]  W. W. Peterson,et al.  Error-Correcting Codes. , 1962 .

[6]  Chin-Liang Wang,et al.  Systolic array implementation of multipliers for finite fields GF(2/sup m/) , 1991 .

[7]  Gui Liang Feng.  A VLSI Architecture for Fast Inversion in GF(2^m) , 1989, IEEE Trans. Computers.

[8]  Trieu-Kien Truong,et al.  Systolic Multipliers for Finite Fields GF(2m) , 1984, IEEE Transactions on Computers.

[9]  Mario Kovac,et al.  SIGMA: a VLSI systolic array implementation of a Galois field GF(2 m) based multiplication and division algorithm , 1993, IEEE Trans. Very Large Scale Integr. Syst..

[10]  Stafford E. Tavares,et al.  A Fast VLSI Multiplier for GF(2m) , 1986, IEEE J. Sel. Areas Commun..

[11]  H. T. Kung,et al.  Fault-Tolerance and Two-Level Pipelining in VLSI Systolic Arrays , 1983 .

[12]  S. Kung,et al.  VLSI Array processors , 1985, IEEE ASSP Magazine.

[13]  Trieu-Kien Truong,et al.  VLSI Architectures for Computing Multiplications and Inverses in GF(2m) , 1983, IEEE Transactions on Computers.

[14]  Shyue-Win Wei,et al.  VLSI architectures for computing exponentiations, multiplicative inverses, and divisions in GF(2/sup m/) , 1997 .

[15]  Dorothy E. Denning,et al.  Cryptography and Data Security , 1982 .

[16]  John V. McCanny,et al.  Use of unidirectional data flow in bit-level systolic array chips , 1986 .

[17]  Vijay K. Bhargava,et al.  Bit-Serial Systolic Divider and Multiplier for Finite Fields GF(2^m) , 1992, IEEE Trans. Computers.