Dual-band CDR using a half-rate linear phase detector

This paper describes a dual-band clock and data recovery circuit using a new half-rate linear phase detector. With the proposed sampling scheme, the phase detector produces UP/DN signals with equal pulsewidth and thus eliminates the demand of current scaling in the charge pump. The test chip fabricated by CMOS 0.18 μm 1P6M process can operate at 2.7 and 1.62 Gbps which satisfies the DisplayPort standard. It can recover the NRZ data of a (27-1) PRBS with a bit error rate less than 10−12. The chip core occupies an area of 0.36 mm2. The power consumption is 50 mW at 2.7 Gbps with a 1.8 V supply voltage.

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