A low-power pipelined MAC architecture using Baugh-Wooley based multiplier
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[1] Magnus Själander,et al. High-speed and low-power multipliers using the Baugh-Wooley algorithm and HPM reduction tree , 2008, 2008 15th IEEE International Conference on Electronics, Circuits and Systems.
[2] David G. Chinnery,et al. Low power multiplication algorithm for switching activity reduction through operand decomposition , 2003, Proceedings 21st International Conference on Computer Design.
[3] Harish M. Kittur,et al. Low power energy efficient pipelined multiply-accumulate architecture , 2012, ICACCI '12.
[4] Tung Thanh Hoang,et al. High-speed, energy-efficient 2-cycle Multiply-Accumulate architecture , 2009, 2009 IEEE International SOC Conference (SOCC).
[5] Mary Sheeran,et al. Multiplier reduction tree with logarithmic logic depth and regular connectivity , 2006, 2006 IEEE International Symposium on Circuits and Systems.
[6] Vasily G. Moshnyaga. Reducing Switching Activity of Subtraction via Variable Truncation of the Most-Significant Bits , 2003, J. VLSI Signal Process..
[7] C. Luchini,et al. [High speed]. , 1969, Revista De La Escuela De Odontologia, Universidad Nacional De Tucuman, Facultad De Medicina.