Low-Phase Noise Clock Distribution Network Using Rotary Traveling-Wave Oscillators and Built-In Self-Test Phase Tuning Technique

This brief describes a built-in self-test (BIST) technique used to verify and tune the timing integrity of a clock distribution system implemented with injection-locked rotary traveling-wave oscillators (RTWOs). The die is fabricated in a 130-nm CMOS process and occupies 4.4 mm × 2.25 mm and is limited by the outer diameter of the RTWOs, leaving internal space for other circuits. The BIST circuits take a chip area of only 0.025 mm2. The measured frequency tuning range of the RTWOs is from 1.7 to 2.0 GHz. The measured RTWO phase tuning range is 58.56° with a worst case 0.34° phase tuning resolution. The injection-locked clock multiplication and distribution network achieves a single-sideband integrated RMS jitter of 66.8 fs from 10-kHz to 40-MHz offset frequencies at 2.04-GHz output. The BIST circuit allows testing of the integrity of the clock distribution system at speed by determining if the system clock skew can be tolerated or needs adjustment. To the authors' knowledge, the implementation of this BIST technique to determine clock integrity of an injection-locked clock distribution network has not been explored previously.

[1]  Saleh Osman,et al.  Phase-Noise Analysis in Rotary Traveling-Wave Oscillators Using Simple Physical Model , 2010, IEEE Transactions on Microwave Theory and Techniques.

[2]  Shen-Iuan Liu,et al.  A 2.4-GHz Subharmonically Injection-Locked PLL With Self-Calibrated Injection Timing , 2012, IEEE Journal of Solid-State Circuits.

[3]  SeongHwan Cho,et al.  A 14.2 mW 2.55-to-3 GHz Cascaded PLL With Reference Injection and 800 MHz Delta-Sigma Modulator in 0.13 $\mu$m CMOS , 2012, IEEE Journal of Solid-State Circuits.

[4]  Ying Liu,et al.  Impact of interconnect variations on the clock skew of a gigahertz microprocessor , 2000, DAC.

[5]  Koji Takinami,et al.  Phase Error Calibration Technique for Rotary Traveling Wave Oscillators , 2010, IEEE Journal of Solid-State Circuits.

[6]  Hui Wu,et al.  A 1V, 1mW, 4GHz Injection-Locked Oscillator for High-Performance Clocking , 2007, 2007 IEEE Custom Integrated Circuits Conference.

[7]  Zhanjun Bai,et al.  A novel Injection Locked Rotary Traveling Wave Oscillator , 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

[8]  Ralph Mason,et al.  Complete SOC Transceiver in 0.18 $\mu$m CMOS Using Q-Enhanced Filtering, Sub-Sampling and Injection Locking , 2012, IEEE Journal of Solid-State Circuits.

[9]  S. Naffziger,et al.  A 90-nm variable frequency clock system for a power-managed itanium architecture processor , 2006, IEEE Journal of Solid-State Circuits.

[10]  Ralph Mason,et al.  Complete SOC transceiver in 0.18µm CMOS using Q-enhanced filtering, sub-sampling and injection locking , 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

[11]  Jiang Hu,et al.  Integrated Placement and Skew Optimization for Rotary Clocking , 2006 .

[12]  W. P. Robins.  Phase Noise in Signal Sources: Theory and applications , 1984 .

[13]  Alan N. Willson,et al.  A 2.8–3.2-GHz Fractional- $N$ Digital PLL With ADC-Assisted TDC and Inductively Coupled Fine-Tuning DCO , 2013, IEEE Journal of Solid-State Circuits.

[14]  Takamaro Kikkawa,et al.  A ring-VCO-based sub-sampling PLL CMOS circuit with −119 dBc/Hz phase noise and 0.73 ps jitter , 2012, 2012 Proceedings of the ESSCIRC (ESSCIRC).