Patching Method for Lookup-Table Type FPLs

Field programmable gate arrays (FPGA) make rapid prototyping an easier task, and are useful in many applications due to their growing speed and capacity. In this paper, we present a rectification method for lookup-table type FPGA's. Instead of changing the netlist of a circuit, we only modify the functionality realized by look-up tables and keep the netlist equal so that there will be no change in the delay of the circuit. We formulate the problem using characteristic functions and present a redesign method based on Boolean relation techniques.

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