Distributed scheduling of resources on interconnection networks

In this paper, we have studied the distributed scheduling of resources on interconnection networks. The resource scheduling problem is different from the conventional address mapping problem on interconnection networks because a request is not directed towards a particular destination address but to any one of a pool of destination addresses for free resources. To design an algorithm with the minimum transfer of control signals, priority is associated with the scheduling of multiple requests. This is illustrated by the distributed cross-bar switch which has one signal line in each direction of a switch node. For complete asynchronous operation, more signal lines are needed. This is illustrated by the distributed Omega and binary n-cube networks. Each exchange box in the network operates independently to resolve conflicts. The performance of the distributed scheduling algorithm for the Omega and cube networks is compared against the optimal centralized scheduling algorithm which has about 1% average blocking probability. The performance degradation is less than 20% in all cases. The theory of the design can be applied to other interconnection networks.

[1]  G. Jack Lipovski,et al.  HARDWIRED RESOURCE ALLOCATORS FOR RECONFIGURABLE ARCHITECTURES. , 1980 .

[2]  Stephen F. Lundstrom,et al.  Design and Validation of a Connection Network for Many-Processor Multiprocessor Systems , 1981, Computer.

[3]  William C. McDonald,et al.  The Advanced Data Processing Testbed , 1978, COMPSAC.

[4]  David J. Kuck ILLIAC IV Software and Application Programming , 1968, IEEE Transactions on Computers.

[5]  William R. Crowther,et al.  Pluribus: a reliable multiprocessor , 1975, AFIPS '75.

[6]  Kenneth E. Batcher STARAN parallel processor system hardware , 1974, AFIPS '74.

[7]  Kenneth E. Batcher,et al.  The flip network in staran , 1976 .

[8]  Tse-Yun Feng,et al.  On a Class of Multistage Interconnection Networks , 1980, IEEE Transactions on Computers.

[9]  Gordon Bell,et al.  C.mmp: a multi-mini-processor , 1972, AFIPS '72 (Fall, part II).

[10]  Duncan H. Lawrie,et al.  Access and Alignment of Data in an Array Processor , 1975, IEEE Transactions on Computers.

[11]  Harold S. Stone,et al.  Parallel Processing with the Perfect Shuffle , 1971, IEEE Transactions on Computers.

[12]  Robert J. McMillen,et al.  Using the Augmented Data Manipulator Network in PASM , 1981, Computer.

[13]  Janak H. Patel Performance of Processor-Memory Interconnections for Multiprocessors , 1981, IEEE Transactions on Computers.

[14]  G. Jack Lipovski,et al.  A hardware support mechanism for scheduling resources in a parallel machine environment , 1981, ISCA '81.

[15]  Marshall C. Pease,et al.  The Indirect Binary n-Cube Microprocessor Array , 1977, IEEE Transactions on Computers.

[16]  G. Jack Lipovski,et al.  An overview of the Texas reconfigurable array computer , 1899, AFIPS '80.

[17]  Tse-Yun Feng Data Manipulating Functions in Parallel Processors and Their Implementations , 1974, IEEE Transactions on Computers.

[18]  Mark A. Franklin,et al.  VLSI Performance Comparison of Banyan and Crossbar Communications Networks , 1981, IEEE Transactions on Computers.

[19]  Robert J. McMillen,et al.  The Cube Network as a Distributed Processing Test Bed Switch , 1981, ICDCS.