论文信息 - ep Trench Isolation for CMOS Image S

ep Trench Isolation for CMOS Image S

This paper proposes the integration of MOS Trench Isolation (CDTI) as a solution to boos pixels performances. We have investigat compared it to oxide-filled Deep Trench configurations, on silicon samples, with a fabr TCAD simulations. The experiment measure on CDTI without Sidewall Implantation (SW low dark current (~1aA at 60°C for a 1.4µ full-well capacity (~12000e-), and it shows qua improvement compared to DTI configuratio optimized CDTI gate oxide thickness hav comparable angular response to oxide-filled DT

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